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| PRELIMINARY PRODUCT SPECIFICATION 2.4GHz wireless audio streamer FEATURES * * * * * * * * * * * * * * Low cost 0.18u CMOS process, 36 pin 6x6mm QFN package Single chip 2.4GHz RF transceiver 4Mbit/sec RF link Input sample rate up to 96kHz, 24bits Output sample rate up to 48kHz, 16bits Programmable latency Quality of Service engine supporting up to 1.536 Mbit/s LPCM audio S/PDIF interface for direct connection to PC soundcard and surround receivers I2S interface for glueless audio support SPI or 2-wire interface for up to 12 kbit/sec peak bidirectional digital control/AUX data On chip optional 2:1 compression On chip voltage regulators Few external components Uses global 2.4GHz band NRF24Z1 APPLICATIONS * * * * * * * * * Compact Disk, CD quality headset MP3 / Mini Disk headset Speakers Surround speakers Microphone Musical instruments Audio streaming from PC soundcard to HiFi system Download MP3 files from PC to MP3 player Compressed video streaming GENERAL DESCRIPTION NRF24Z1 gives you a true single chip system for CD quality audio streaming of up to16 bit 48 kHz audio with support of up to 24 bit 96 kHz input. I2S and S/PDIF interfaces are supported for audio I/O. Seamless interfacing of low cost A/D and D/A for analog audio input and output. SPI or 2-wire (I2C compatible) serial interfaces for control. The circuit has embedded voltage regulators, giving maximum noise immunity and operation from a single 2.0V to 3.6V supply. QUICK REFERENCE DATA Parameter Minimum supply voltage Temperature range Peak supply current in transmit @ -5dBm output power Peak supply current in receive mode Supply current in power down mode Maximum transmit output power Audio sample rate Audio resolution Receiver sensitivity Value 2.0 -20 to +80 15 32 4 0 32, 44.1 or 48 16 -80 Unit V C mA mA A dBm kbps bit dBm Table 1-1 NRF24Z1 quick reference data. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 1 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer ORDERING INFORMATION Type number NRF24Z1 NRF24Z1-EVKIT Description 36L QFN 6x6 mm Evaluation kit Version A 1.0 Table 1-2 NRF24Z1 ordering information. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 2 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer TABLE OF CONTENTS FEATURES ............................................................................................................................1 APPLICATIONS ....................................................................................................................1 GENERAL DESCRIPTION ...................................................................................................1 QUICK REFERENCE DATA ................................................................................................1 ORDERING INFORMATION ...............................................................................................2 TABLE OF CONTENTS........................................................................................................3 1 Pin Assignment ...............................................................................................................6 2 Pin Function....................................................................................................................7 3 Glossary of terms ............................................................................................................8 4 Architectural Overview...................................................................................................9 4.1 Audio transmitter ..................................................................................................11 4.1.1 I2S audio input ..............................................................................................11 4.1.2 S/PDIF audio input .......................................................................................12 4.1.3 Serial control (slave) interfaces.....................................................................12 4.1.4 Master interfaces...........................................................................................12 4.1.5 Direct data input pins ....................................................................................13 4.1.6 Interrupt output .............................................................................................13 4.2 Audio Receiver .....................................................................................................13 4.2.1 I2S audio output ............................................................................................14 4.2.2 S/PDIF audio output .....................................................................................15 4.2.3 Master interfaces...........................................................................................15 4.2.4 Serial control (slave) interfaces.....................................................................15 4.2.5 Parallel port and PWM..................................................................................15 4.3 Blocks common to audio transmitter and receiver................................................16 4.3.1 XTAL Oscillator...........................................................................................16 4.3.2 Radio Transceiver .........................................................................................16 4.3.3 Quality of Service engine..............................................................................16 4.3.4 Audio compression / Decompression ...........................................................17 4.3.5 Power ............................................................................................................17 4.3.6 IREF / RESET...............................................................................................17 5 Operation overview.......................................................................................................18 5.1 Power on / RESET sequence ................................................................................18 5.2 RF Link initialization............................................................................................18 5.2.1 Idle state ........................................................................................................18 5.2.2 Link-locate state ............................................................................................19 5.2.3 Synchronization state ....................................................................................19 5.3 Audio streaming....................................................................................................19 5.4 Audio receiver clock rate recovery.......................................................................20 5.5 Data link................................................................................................................20 5.6 Power down mode.................................................................................................21 6 NRF24Z1 register MAP.................................................................................................22 6.1 Access from audio transmitter side.......................................................................22 6.2 Access from audio receiver side ...........................................................................22 7 Digital I/O .....................................................................................................................25 7.1 Digital I/O behaviour during RESET....................................................................25 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 3 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7.2 Audio interfaces ....................................................................................................25 7.3 I2S Audio Interface...............................................................................................25 7.4 S/PDIF Audio Interface ........................................................................................26 7.5 Audio interface functionality ................................................................................27 7.5.1 ATX audio interface control .........................................................................27 7.5.2 ARX audio interface control.........................................................................30 7.5.3 I2S Audio interface timing............................................................................32 7.6 Serial master interfaces .........................................................................................33 7.6.1 Timing serial master interfaces....................................................................36 7.7 Control and GPIO interfaces.................................................................................37 7.7.1 ATX control and GPIO pins .........................................................................37 7.7.2 SPI slave interface.........................................................................................38 7.7.3 2-wire slave interface....................................................................................38 7.7.4 General purpose input pins D[2:0]................................................................40 7.7.5 ATX Control interface timing.......................................................................41 7.7.6 ARX control interface options ......................................................................42 7.7.7 ARX GPIO pins ............................................................................................43 7.8 Data Channel Timing............................................................................................45 7.8.1 Forward data channel, data transfer from ATX to ARX...............................45 7.8.2 Return data channel, data transfer from ARX to ATX .................................46 8 Quality of service (Qos) and RF ...................................................................................48 8.1 Link algorithm.......................................................................................................48 8.2 RF protocol ...........................................................................................................48 8.3 Adaptive frequency hopping.................................................................................48 8.3.1 Adapting to the RF environment...................................................................50 8.4 Link registers.........................................................................................................50 8.4.1 RF link latency..............................................................................................52 8.5 RF output power ...................................................................................................53 9 Interrupts .......................................................................................................................54 10 RESET outputs..........................................................................................................55 11 Power down control ..................................................................................................56 11.1 Enter power down.................................................................................................56 11.2 Wake up from power down...................................................................................56 11.2.1 External pin change.......................................................................................57 11.2.2 Timer controlled wake up .............................................................................57 11.3 NRF24Z1 power saving example ..........................................................................58 12 Register update over the data link.............................................................................60 13 Eletrical Specification...............................................................................................61 14 Absolute maximum ratings .......................................................................................63 15 Package outline .........................................................................................................64 16 Application Information............................................................................................65 16.1 Antenna I/O...........................................................................................................65 16.2 Crystal Specification.............................................................................................65 16.3 Bias reference resistor...........................................................................................65 16.4 Internal digital supply de-coupling .......................................................................65 16.5 PCB layout and de-coupling guidelines................................................................66 17 Application example .................................................................................................67 17.1 NRF24Z1 schematics.............................................................................................67 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 4 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 17.2 17.3 18 19 20 NRF24Z1 layout ....................................................................................................69 NRF24Z1 Bill of Material .....................................................................................71 References.................................................................................................................73 Definitions.................................................................................................................74 Your notes.................................................................................................................75 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 5 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 1 PIN ASSIGNMENT MMOSI MMISO IRQ/ DO[3]/ PWM 36 MSCK 35 MCSN MSCL VDD VSS 34 VSS 33 32 31 30 29 28 SSEL/DO[2] 1 27 MSDA SMISO/SSDA/DO[1] 2 26 MODE NRF24Z1 SSCK/SSCL/DO[0] 3 25 VSS QFN36 6x6 SCSN/SADR/DI[3] 4 24 IREF VDD 5 23 VSS_PA SMOSI/DD[2]/DI[2] 6 22 ANT2 DD[1]/DI[1] 7 21 ANT1 DD[0]/DI[0] 8 20 VDD_PA REQ 9 19 VDD 10 CLK 11 WS 12 DATA 13 SPDIO 14 MCLK 15 DVDD 16 VSS 17 XC2 18 XC1 Figure 1-1: Pin assignment NRF24Z1 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 6 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 2 Pin PIN FUNCTION Name Slave IF SSEL ARX GPIO DO[2] Pin function Slave IF Dig. In ARX GPIO IF Dig. Out Description ARX with GPIO IF ATX/ARX with slave IF Slave interface select GPIO out bit #2 1: 2-wire, 0: SPI Slave SPI serial out GPIO out bit #1 / Slave 2-wire data (bidir) Slave SPI clock GPIO out bit #0 / Slave 2-wire clock Slave SPI slave select GPIO in bit #2 / Address select 2-wire slave Power Supply (2.0 -3.6 V DC) Slave SPI serial in GPIO in bit #3 / Direct data in bit #2 Direct data in bit #1 GPIO in bit #1 Direct data in bit #0 GPIO in bit #0 I2S data request (programmable polarity) I2S bit clock I2S word clock I2S data signal S/PDIF interface 256X sample rate clock to ADC or DAC Digital voltage regulator output for decoupling Ground (0V) Crystal Pin 2 Crystal Pin 1 Power Supply (2.0 -3.6 V DC) DC output (+1.8V) for RF interface (ANT1, ANT2) Antenna interface 1 Antenna interface 2 Ground (0V) Connection to external Bias reference resistor, or RESET if pulled to VDD Ground (0V) NRF24Z1 function 1 : audio transmitter, 0: audio receiver Master 2-wire bi-directional data Master 2-wire bi-directional clock Master SPI primary slave select (active low) Master SPI serial input Master SPI serial output Ground (0V) Power Supply (2.0 -3.6 V DC) Ground (0V) Master SPI clock Interrupt request GPIO out bit #3 / PWM output 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SMISO DO[1] /SSDA SSCK DO[0] /SSCL SCSN DI3 /SADR VDD SMOSI DI2 /DD[2] DD[1] DI1 DD[0] DI0 REQ CLK WS DATA SPDIO MCLK DVDD VSS XC2 XC1 VDD VDD_PA ANT1 ANT2 VSS_PA IREF VSS MODE MSDA MSCL MCSN MMISO MMOSI VSS VDD VSS MSCK IRQ DO[3] / PWM Digital Output / Digital IO Dig. In Dig. Out Digital Input Power Digital Input Digital Input Digital Input Dig. Out Dig. In Dig. In Dig. Out Dig. In Dig. Out Dig. In Dig. Out Dig. In Dig. Out Dig. Out Regulator output Power Analog output Analog input Power Regulator output RF RF Power Analog input Power Digital Input Digital IO Digital IO Digital Output Digital Input Digital Output Power Power Power Digital Output Digital Output Table 2-1 NRF24Z1 pin function Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 7 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 3 GLOSSARY OF TERMS Term ADC ARX ATX CD CHPA CLK CPOL CRC DAC DSP EEPROM Flash GFSK GPIO I2S ISM LPCM MBZ MCU MP3 PWM QOS RX S/PDIF SPI TX 2-wire Description Analog to Digital Converter audio receiver audio transmitter Carrier Detect SPI clock phase Clock SPI clock polarity Cyclic Redundancy Check Digital to Analog Converter Digital Signal Processor electrical erasable programmable read only memory Flash memory Gaussian Frequency Shift Keying General Purpose In Out 3 wire audio serial interface Industrial-Scientific-Medical linear PCM (pulse code modulation) Must Be Zero (reserved for future extensions) Micro Controller Unit a popular compressed audio format Pulse Width Modulation Quality Of Service Receive one wire serial digital audio format Serial Peripheral Interface Transmit 2-wire serial interface compatible with I2C Table 3-1 Glossary of terms NRF24Z1. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 8 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 4 ARCHITECTURAL OVERVIEW NRF24Z1 is a 4 MBit/s single chip RF transceiver that operates in the world wide 2.4 GHz licencee free ISM band. The nR24Z1 is based on the proven nRF24xx radio and ShockBurstTM platforms from Nordic Semiconductor. The device offers a wireless channel for seamless streaming of LPCM or compressed audio in parallel with a low data rate control channel. To enable this, the device offers the following features in addition to the nRF24xx RF platform: * * * * Standard digital audio interfaces (I2S, S/PDIF) Fully embedded Quality of Service engine that handles all RF protocol and RF link tasks. SPI and 2-wire master and slave control interfaces GPIO pins As all processing related to audio I/O, RF protocol and RF link management is embedded, the device offers the end application an up to 1.54 MBit/s transparent audio channel without any true time processing needed. NRF24Z1 can be utilized in systems without external microcontroller or by a simple microcontroller that only need to handle low speed tasks over the serial or parallel ports (ex: volume up/down). A typical system using NRF24Z1 can be seen in Figure 4-1 Audio Source Destination SPI Storage DSP / uP I2S NRF24Z1 NRF24Z1 MCLK I2S SPI DAC and audio amplifier Audio transmitter Audio receiver E2 Figure 4-1 Typical audio application using NRF24Z1 In this system a DSP or micro controller feeds data from storage to NRF24Z1 using standard audio format (I2S). A NRF24Z1 pair transfers the audio data and presents it to a stereo DAC on the other side. For other parts of the application, the NRF24Z1 link will in other words look like an open channel (like a cable). Initial configuration of NRF24Z1 is done by the micro controller through a SPI or 2-wire control interface. On the destination side, peripherals like a DAC can be controlled from the audio source side through the control channel offered by NRF24Z1. In designs without an external micro controller, configuration data can be loaded by NRF24Z1 from an optional EEPROM/FLASH memory, enabling it to operate stand alone with limited feature set. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 9 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer A wireless system that is streaming audio will have a very asymmetrical load on the RF link since audio data is fed from an audio source (CD player) to a destination (loud speakers). From the destination back to the audio source only service and control communication is needed. NRF24Z1 are used both on the audio source side (ex. in a CD player) transmitting audio data, and in the 'destination' (loud speaker) side receiving audio data. Due to the asymmetry, NRF24Z1 has two main modes set by external pin MODE, depending on which side of the link it is put. The two modes have significant differences both in internal and I/O functionality. To ease understanding of NRF24Z1 operation, the following notation is introduced: * Audio transmitter (ATX) - NRF24Z1 on the audio source side, transmitting audio data * Audio receiver (ARX ) - NRF24Z1 on the destination side, receiving audio data Transmitter and receiver are here referring to the flow of the audio; the NRF24Z1 RF front end always runs a full two way link. The NRF24Z1 control and data channel is a two way low data rate channel superimposed on the audio and service communication. The audio transmitter is designated master meaning that when a RF link is present 2-wire, SPI, GPIO and internal registers in the audio receiver can be seen and controlled as a virtual extension of the audio transmitters own I/O and registers. The implications of this is that external devices like audio DAC or volume control components connected to the audio receiver effectively can be controlled by input to the audio transmitter. User actions (ex: push of a button) on the audio receiver side are similarly fed back to and can be processed on the audio transmitter side. The following sections will give an overview of the I/O, main modules and functionality of NRF24Z1. Due to the differences in ATX and ARX, the overview will present the modes separately. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 10 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 4.1 Audio transmitter When NRF24Z1 is put at the audio source side of the RF link, MODE must be high and NRF24Z1 becomes an audio transmitter (ATX). The block schematic of NRF24Z1 in ATX mode can be seen in Figure 4-2. Local Status POWER VDD DVDD VSS SADR/ SCSN SSCL/ SSCK SSDA/ SMISO SMOSI/ DD[2] SSEL DD[1:0] IRQ SPDIO CLK DATA WS REQ 2-wire master MSDA MSCL MMISO MSCK MMOSI MCSN Local Config Remote Status Remote Config Remote Data SPI master Slave IF MUX 2-wire slave SPI slave TDM QOS nRF 24xx radio VSS_PA ANT1 ANT2 VDD_PA S/PDIF to I2S Serial to parallel Audio compress MUX BIAS / RESET IREF MCLK PLL Clock Control XTAL oscillator XC2 XC1 Figure 4-2 NRF24Z1 ATX mode block diagram The I2S or S/PDIF interfaces can be used for audio data input or alternatively the device may stream other real-time data from a DSP over the I2S interface. 4.1.1 I2S audio input For seamless input from audio sources physically close to NRF24Z1, I2S is the preferred interface. The I2S interface consists of pins CLK, DATA and WS. The interface supports Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 11 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer sample rates of 32, 44.1, 48 and 96 kHz. Data may be in 16, 20 or 24 bit format. 1 The data rate is automatically detected. I2S may also be used with an external stereo ADC for analog audio sources. The NRF24Z1 offers a 256 times audio sampling rate clock (fS) on the MCLK pin to be used as system clock for the ADC. A REQ output is available for pacing the data-flow when streaming MP3 and other "data" streams over the I2S interface. 4.1.2 S/PDIF audio input For audio sources physically more remote, the ATX offers a (CMOS level) S/PDIF input on pin SPDIO. This interface supports 32, 44.1 or 48 kHz sampling rates with resolution of 16, 20 or 24 bit. It supports both linear and nonlinear audio according to IEC standards, see ch. 7.4 for details. 4.1.3 Serial control (slave) interfaces When ATX is controlled by an external MCU, configuration and control data both for the audio transmitter itself and a linked audio receiver may be entered via a 2-wire or SPI slave serial interface. The same interface is used for reading back status information. The register map is identical for both interfaces, but only one of the interfaces, selected by SSEL pin, may be used in a given application. The two interfaces are : SSEL = 0; SPI (pins SCSN, SSCK, SMISO, SMOSI). SSEL = 1; 2-wire (pins SADR, SSCL and SSDA) Pin SADR is not part of a standard 2-wire interface but selects one of two possible bus addresses for the NRF24Z1. 4.1.4 Master interfaces For standalone operation of NRF24Z1, a serial EEPROM or FLASH memory may be connected to a SPI or 2-wire master interface. If a memory is present at any of these interfaces during power up or reset, the device will read default configuration data from the memory. The SPI master is found on pins MCSN, MMISO, MMOSI and MSCK and 2-wire master on pins MSDA and MSCL. 1 This specification item is for the I2S input interface. Not all of these formats can be transferred within the available 1.54 Mbit/s data rate. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 12 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 4.1.5 Direct data input pins The ATX has 2 general purpose input pins, DD[1:0], that may be transmitted directly to and hence mirrored on the audio receiver. When SSEL is set high (2-wire interface selected), one additional direct data pin (DD[2]) is available. If the logic level on pins DD[2:0] are mirrored (copied) over the control link, pins DO[2:0] on the audio receiver will carry the mirrored signal. These pins may hence be used to switch on/off audio receiver peripherals without microprocessor activity. 4.1.6 Interrupt output The NRF24Z1 can interrupt the external application through pin IRQ based on a number of sources such as no audio input detected, loss of RF communication etc. Once IRQ has triggered external MCU, interrupt status can be read, through the serial control interface. 4.2 Audio Receiver When NRF24Z1 is put at the destination side of the RF link, MODE must be low and NRF24Z1 becomes the audio receiver (ARX). The block schematic of NRF24Z1 in ARX mode can be seen in Figure 4-3. I2S or S/PDIF are now used for audio or other real time data output. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 13 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer VDD DVDD VSS 2-wire master POWER MSDA MSCL SPI master MMISO MSCK MMOSI MCSN VSS_PA ANT1 ANT2 VDD_PA nRF 24xx radio DI[3:0] TDM QOS MUX PWM I2S to SPDIF DO[3:0] SPDIO CLK DATA WS REQ MUX IREF BIAS / RESET Audio decompress Parallel to serial XC2 XC1 XTAL oscillator Clock Control PLL / MUX MCLK Figure 4-3 NRF24Z1 ARX mode block diagram After a link is established the user can control the SPI and 2 wire master from the audio transmitter. In this way the audio transmitter is able to control audio receiver serial peripherals like audio DACs and amplifiers. 4.2.1 I2S audio output Audio output to devices physically close to NRF24Z1 (typically a stereo DAC) are normally driven by the I2S output (pins CLK, DATA and WS). The interface supports sample rates of 32, 44.1 and 48 kHz. Data are in 16 bit format. In audio receiver mode the MCLK pin provides 256 times fS clock for an external DAC. A REQ input is available for pacing the data-flow when streaming MP3 or other "data" streams over the I2S. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 14 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 4.2.2 S/PDIF audio output For physically more remote audio devices, the audio receiver provides an S/PDIF (full swing CMOS) output on pin SPDIO. This interface supports 32, 44.1 and 48 kHz, 16 or 24 bit data. It supports both linear and nonlinear audio according to IEC standards, see ch. 7.4 for details. 4.2.3 Master interfaces A serial EEPROM or FLASH memory ma y be connected to a SPI or 2-wire master interface. If a memory is present at any of these interfaces during power up or reset, the device will read default configuration data from that memory; otherwise hard coded default values will be used. During audio receiver configuration, the SPI master (pins MMSCK, MMISO, MMOSI, MCSN) is operated at 1MHz or 0.5MHz with the SPI format set to CPOL=0,CHPA=0 for EEPROM/FLASH compatibility. After a link is established, the user may control the SPI master from the audio transmitter. The available clock speed is up to 8 MHz over the full operation range of the device. During start-up, the audio receiver operates the 2-wire master (MSDA, MSCL) interface at 100 kHz. After a link is established, the user may control the 2-wire master from the audio transmitter to 100kHz, 400kHz or 1MHz. 4.2.4 Serial control (slave) interfaces When ARX is controlled by an external MCU, configuration and control data for the audio receiver may be entered via a 2-wire or SPI slave serial interface. The same interface is used for reading back status information. The register map is identical for both interfaces, but only one of the interfaces, selected by SSEL pin, may be used in a given application. The two interfaces are : SSEL = 0; SPI (pins SCSN, SSCK, SMISO, SMOSI). SSEL = 1; 2-wire (pins SADR, SSCL and SSDA) Pin SADR is not part of a standard 2-wire interface but selects one of two possible bus addresses for the NRF24Z1. 4.2.5 Parallel port and PWM Alternatively to the serial slave interfaces, ARX can be configured with an 8 bit parallel port, which can be controlled and read from the audio transmitter. There are 4 input pins DI[3:0] that are continuously monitored when a link is up. Changes on any of these inputs will be sent back to the audio transmitter where it can be accessed in a register (via the serial control interface). The audio receiver can also be programmed to wake up from power down mode on a change on one of these pins. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 15 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer There are 4 outputs DO[3:0] that are controlled from the audio transmitter. Any of these may be programmed for high current in order to drive LEDs or for standard CMOS to control of other devices on the audio receiver board. DO3 may be programmed to output a PWM signal, where the output duty cycle is programmable with 8-bit resolution from the audio transmitter. Note that this PWM cannot be used as audio DAC The output pins DO[3:0] may also function as slave select signals if multiple slaves are present on the ARX SPI master bus. 4.3 Blocks common to audio transmitter and receiver 4.3.1 XTAL Oscillator The crystal oscillator will provide a stable reference frequency with low phase noise for the radio and audio functions. See section 16.2 for full Crystal Specification. 4.3.2 Radio Transceiver The RF transceiver part of the circuit is a member of nRF24xx family of low power highly integrated 2.4GHz ShockBurstTM transceivers. The transceiver interface is optimized for high speed streaming of up to 4 Mbps. Output power and some protocol parameters can be controlled by the user via the QoS module. 4.3.3 Quality of Service engine The primary function of the quality of service engine is to deliver a robust communication channel between the audio transmitter and audio receiver in an audio streaming application. Several data streams with different properties are handled. The available bandwidth is shared between audio data, service data and remote data. Data integrity is ensured through a number of RF protocol features: 1. Packets of data are sent in frames and integrity of each packet is ensured as every packet has a complete build of RF address, payload and CRC. 2. Packets that are lost or received with errors are handled by the error correction level of the quality of service engine; a two way, acknowledge protocol: When a packet is received by ARX, it's registered and CRC is checked. After ARX has received a frame it sends a packet back to ATX acknowledging the packets that where successfully transferred. Packets lost or received with errors will be re-sent from ATX in the next frame. 3. Finally the information (audio data) is spread over the 2.4 GHz band by use of an adaptive frequency hopping algorithm. Through this a NRF24Z1 link can handle RF propagation challenges like reflections and multi-path fading and not least avoid Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 16 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer heavily trafficked areas of the 2.4 GHz band. The 2.4 GHz band is a world wide open RF band and co-existence with RF systems such as Bluetooth, ZigBee, WLAN/WiFi as well as other nRF applications, is increasingly important. NRF24Z1 constantly monitors the quality of the RF link and numbers indicating total link quality are available for external control devices in registers. NRF24Z1 can also be set to interrupt external controller devices upon poor link quality before RF link is lost. An external controller device can hence take further actions to improve link quality or warn end user if RF link margins are poor. The secondary function of the QoS module is to run a link initialization algorithm which manages initial connect and re-connect if link is lost (ex: out of range) between paired NRF24Z1's. Several schemes are available to enable NRF24Z1 connection without end user involvement. 4.3.4 Audio compression / Decompression Default operation for NRF24Z1 is streaming of uncompressed audio, however there is some optional low delay audio compression options available. This function can be enabled by the user to conserve power or to increase the dynamic range with a constant signal to noise ratio for 24-bit input signals. 4.3.5 Power The power section of NRF24Z1 offers linear regulated supply to all internal parts of the device. This makes the device very robust towards external voltage supply noise and isolates (audio) devices in an application from noise generated the NRF24Z1. 4.3.6 IREF / RESET The IREF pin sets up the bias reference for the NRF24Z1 by use of an external resistor. Pulling IREF to VDD will reset the device. When IREF pin is released, NRF24Z1 runs a full configuration procedure. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 17 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 5 OPERATION OVERVIEW 5.1 Power on / RESET sequence When supply is applied, NRF24Z1 goes into power on reset. The reset is held until supply voltage is kept above minimum supply voltage for a few milliseconds. Pulling IREF to VDD will also put the device into reset. When reset (power on or IREF high) is released the device needs to be configured. There are 2 ways NRF24Z1 can be configured: 1. After reset NRF24Z1 will look for an external EEPROM/FLASH memory on the SPI master interface. If such a memory is present, configuration data is loaded, which means that all registers values are read from the external memory. If no memory is present on the SPI master interface, the procedure is repeated on the 2-wire master interface. These data will override any initial content of NRF24Z1 registers. 2. If no external memory is present: For both ATX and ARX an external micro processor must configure the NRF24Z1 through the slave SPI or 2-wire serial interface, otherwise hard coded initial register content is used. NOTE: A combination of the two power-up sequences may well be used. One likely scenario is that ATX is configured by external MCU and ARX is configured from an external EEPROM/FLASH memory. NRF24Z1 will now start a link initialization procedure based on the link configuration data. The value of the MODE pin determines whether it will be in ATX or ARX mode. 5.2 RF Link initialization Link-locate Link Synchronization Synchronized Idle Link -lost Link-lost Figure 5-1 : link initialisation algorithm 5.2.1 Idle state The NRF24Z1 link initialsation algorithm will be in its idle state when a link is established, and the channel hopping engine is initiated and synchronized. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 18 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 5.2.2 Link-locate state When the link between ATX and ARX is broken, a special link-locate routine is initiated on both sides to establish a new link, see Figure 5-1. During initialization NRF24Z1 derives a set of channels from register CHP1, CHP2 and CHP3, which will be used during channel hopping in idle state. These channels are also utilized by the link-locate routine when acquiring a feasible startup channel for the new link. - Link-locate on ATX ATX tries to establish a link with ARX by iteratively sending short search packages on all available channels until acknowledge is received from ARX. ATX will send one package on each channel and wait for acknowledge for a specific time which is long enough to secure that ARX has time to respond. The accumulated time used by ATX while looping through all available channels is here defined as the ATX-loop-time. After receiving an acknowledge package from ARX, ATX will enter the synchronization state as described in Figure 5-1. - Link-locate on ARX ARX tries to establish a link with ATX by listening for incoming search packages on all available channels until such is received. When a search package is received, ARX will proceed by sending one acknowledge package to confirm a feasible link. ARX will listen for incoming search packages on each channel for a fixed time which is larger than the ATX-loop-time, which will guarantee at least one search package to get through on each available channel used by ARX, as long as this channel is not being occupied by another radio device. After sending the acknowledge package, ARX will enter the synchronization state. 5.2.3 Synchronization state This state takes care of synchronizing the channel hopping engine on ATX and ARX, to secure that both parts follows the same hopping sequence. ATX takes initiative for starting the channel hopping engine, by sending a start condition to ARX about when to start hopping. Which channel to start from is implicitly found during the link-locate state. 5.3 Audio streaming The audio data fed to the audio interfaces on a NRF24Z1 in ATX mode can be of a number of common digital audio stream formats : I2S (audio serial) interface: * left justified, I2S and right justified S/PDIF interface: * Consumer Linear PCM Audio described in IEC 60958-3. NRF24Z1 has a single ended CMOS interface, so to fulfil the electrical requirements external adaptation circuitry is needed. Phone +4772898900 Fax +4772898989 April 2005 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Page 19 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer * Non-Linear PCM Audio. As described in IEC 61937-1 (General) and IEC 61937-2 (Burst-info). The NRF24Z1 is transparent to the specific audio compression algorithms used, so it covers all the described formats in IEC 61937-3 to 61937-7. In ATX the audio stream formats are converted to the NRF24Z1 RF protocol and transferred over the air. In the ARX the data are validated and converted back to audio stream format and fed to the corresponding audio output interface. 5.4 Audio receiver clock rate recovery In all RF systems streaming `true time' data, maintaining equal datarates on both sides of RF link, is a big challenge. In other words; keeping the master clock (MCLK) for the DAC on the receiving side, equal to the clock used to feed data into the RF device on the transmitter side. If these two clocks are not equal the receiving end will either run out of samples for the DAC or overflow hence need to skip some. Usually this problem is solved by use of very thigh tolerance crystals (expensive) or extensive digital filtering (high current consumption) only masking or interpolating the bits missing in the stream. NRF24Z1 solves this problem without tight tolerance crystal or extensive digital filtering. As long as the NRF24Z1 quality of service engine is able to maintain a RF link, the ARX (audio receiver) locks its master clock output (MCLK) to the speed the audio stream actually is fed into the ATX on. The MCLK signal on the ARX side is hence locked to the reference (crystal) of the device (DSP, MCU, DECODER) feeding the audio data to the ATX and not the crystal of the NRF24Z1 devices (ATX or ARX) themselves. One exception; if the MCLK output option is used in audio transmitter (clocking an external ADC for instance) the crystal on the NRF24Z1 in ATX mode is the reference for the audio speed on the entire NRF24Z1 link. This offers the end application a true loss less audio channel. 5.5 Data link There is a 2-way, low bit rate, robust, control and data link running in parallel with the audio stream. This data link is a part of the quality of service overhead, i.e. difference between on the air data rate (4 MBit/s) and audio data rate 1.5 MBit/s. Data link rate can hence not be traded for higher audio data rate. The functionality of the control and data link is illustrated in Figure 5-2. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 20 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer DI[3:0] DD[2:0] NRF24Z1 ATX mode SPI / 2-wire slave NRF24Z1 ARX mode DO[3:0] SPI / 2-wire master RXDCMD RXWCNT RXRCNT RXDCMD RXWCNT RXRCNT RXWBUF RXWBUF RXRBUF RXRBUF RXEXEC RXEXEC 1: Data for the ARX are fed to the ATX via general purpose inputs or one of the serial slave interfaces 2: The ATX serial slave interfaces gives access to all ATX registers. 3: A sub set of the ATX registers and the input pin status are transferred by RF between two linked NRF24Z1 4: Resulting in a mirror of these ATX registers on the ARX side. The mirrored registers access all ARX RF and audio config plus digital I/O controls and I/O data. 5: Command register contents (like in RXDCMD) dictates the actions to take place on the ARX GPIO pins and serial master interfaces. Input status of general purpose input pins (DI[3:0]) are similarly fed back to ATX. Figure 5-2 NRF24Z1 control and data link Through the control and data link the ATX has full control over all registers related to ARX configuration and can access ARX GPIO (for LED's etc.) and the ARX 2-wire and SPI master interface for configuring of DAC's, volume control and other peripheral functions. 5.6 Power down mode NRF24Z1 has a power saving mode called "Power down". In this mode, the quality of service engine is shut down, and only a low frequency oscillator and some timers are running. The power down mode can be left upon sleep timer time out or on external pin event. The ATX and ARX will now go up and start the link initialization routine as described in section 5.2. The sleep timers also enable the NRF24Z1 to shut down again if no counterpart is found on the air or no audio input is detected. ARX may also be put in and out of power down mode by toggling a pin. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 21 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 6 NRF24Z1 REGISTER MAP NRF24Z1 contains several control and status registers, which are listed in the table below. The registers may be accessed by an external MCU via the (SPI or 2-wire) slave interface. The registers are organized functinally into 6 groups; ATX , Link and ARX control and tatus, and Data link. All registers are present both in audio transmitter and audio receiver. The intial value of all registers is read from EEPROM (if present) immediately after reset, othervise the initial values in Table 6-1 applies. 6.1 Access from audio transmitter side If a MCU on the audio transmitter side writes to a register, the audio transmitter version of the register is written, and registers TXCSTATE, LNKCSTATE, RXCSTAT, RXEXEC controls whether also the audio receiver version of the register is written via the data link. * * * If it is a ATX control register, register TXCSTATE controls if also the audio receiver version of the register is written via the data link If it is a Link control register, register LNKCSTATE controls if also the audio receiver version of the register is written via the data link If it is a ARX control register, register RXCSTATE controls if also the audio receiver version of the register is written via the data link See ch. 12 for details about how control registers are updated via the data link, and Table 7-10 about data link registers. A MCU on the audio transmitter side can read all registers on its side, plus the Link status, ARX status and data link registers, which are read from audio receiver via the data link. 6.2 Access from audio receiver side If a MCU on the audio receiver side writes to a register, only the audio receiver version of the register is written, and it is not sent via the data link to the audio transmitter. Which implies that a MCU on audio transmitter will not know about it, but as mentioned above, ATX MCU may read status registers via the link anytime. A MCU on the audio receiver side can read all registers on its side, but it cannot read anything via the link. In brief ARX MCU only has local access, while ATX MCU controls the data link. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 22 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Hex Register R/W Initial Description Hex R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W R/W R/W R/W 0x40 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0x12 0x05 0x05 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x28 0x00 Table 7-4, page 28 Table 7-15, page 40 Table 9-1, page 54 Table 7-6, page 29 Table 7-5, page 28 Table 8-6, page 53 Table 9-1, page 54 Table 7-6, page 29 Table 7-7, page 30 page 53 page 58 page 58 page 58 page 55 page 60 page 52 page 51 page 51 page 52 page 51 page 51 page 49 ATX registers 0x01 0x20 0x02 0x1A 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x10 0x1B 0x03 0x04 0x05 0x30 0x31 0x32 0x35 0x36 0x37 0x38 0x39 -0x3D 0x3E 0x06 0x07 0x4A 0x41 0x42 0x43 0x44 0x45 0x49 TXSTA TXDD INTSTA TXMOD TXFMT TXLAT INTCF I2SCNF_IN I2SRAT TXPWR TXSTI[0] TXSTI[1] TXWTI TXRESO TXCSTATE LNKSTA LNKQ LNKERR LNKMOD LNKWTH LNKETH CHP1 CHP2 CHP3 ALEN ADDR[0:4] LNKCSTATE RXSTA RXPIN RXMOD RXPIO RXPWME RXPWMD I2SCNF_OUT RXWAKE RXPWR LINK status registers LINK control registers page 48 page 49 page 60 page 42 Table 7-22, page 45 Table 7-8, page 31 Table 7-20, page 44 Table 7-21, page 44 Table 7-21, page 44 Table 7-8, page 31 page 57 page 53 Phone +4772898900 Fax +4772898989 April 2005 ARX status registers ARX control registers Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Page 23 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 0x46 0x47 0x48 0x40 0x4B 0x70 0x71 0x72 0x50-0x5f 0x60-0x6f 0x74 RXSTI[0] RXSTI[1] RXWTI RXRESO RXCSTATE RXDCMD RXWCNT RXRCNT RXWBUF RXRBUF RXEXEC R/W R/W R/W R/W R/W R/W R/W R/W W R W/R 0x00 0x00 0x00 0x00 0x00 0x82 0x00 0x00 0x00 0x00 0x00 page 58 page 58 page 58 page 55 page 60 Table 7-10, page 34 Table 7-11, page 35 Data link registers Table 6-1 NRF24Z1 register listing In the following chapters, the NRF24Z1 registers are described sorted by function. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 24 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7 DIGITAL I/O This section describes the digital I/O pins, control registers and important interface timing of the NRF24Z1. The digital I/O pins of the NRF24Z1 are divided into three groups: 1. Audio interfaces 2. Serial master interfaces 3. Control and GPIO interfaces 7.1 Digital I/O behaviour during RESET During reset all digital pins, except the master SPI interface output pins, are set as inputs to avoid driving conflicts. The master SPI pins MCSN, MSCK and MMOSI are set to output high, that is, in inactive SPI state, ready to read EEPROM configuration data, which is the first thing to happen after reset. All pins will remain in their respective direction until one of the configuration read routines described in section 5.1 is finished, and thereafter I/O pins are set according to new configuration data. 7.2 Audio interfaces The audio interface group are defined as the I2S and S/PDIF interfaces plus the MCLK and REQ pins. Pin name CLK WS DATA MCLK REQ SPDIO Function bit clock word sync clock audio data 256 * audio fundamental sample rate output, see Table 7-4 . data request, used for burst type data, see Table 7-7. S/PDIF serial in- or output, see ch. 7.4. Table 7-1 serial audio port pins 7.3 I2S Audio Interface NRF24Z1 has a three-wire serial audio port which can be configured to be compatible with different serial audio formats. In ATX mode, the audio port is in slave (receive) mode. In ARX mode, the audio port is in master (transmit) mode. The audio port consists altogether of 6 pins, see Table 7-1. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 25 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Figure 7-1 : some serial audio formats audio format Left justified I2S Right Justified I2SCNF[3:0] value 0xA 0x0 0xB Table 7-2 : Example of I2SCNF setting for some common serial audio formats, applies to both I2SCNF_IN and I2SCNF_OUT registers. See also Table 7-7 and Table 7-8. 7.4 S/PDIF Audio Interface NRF24Z1 supports the following formats of the S/PDIF interface: * Consumer Linear PCM Audio described in IEC 60958-3. NRF24Z1 has a single ended CMOS interface, so to fulfil the electrical requirements external adaptation circuitry is needed. Non-Linear PCM Audio, as described in IEC 61937-1 (General) and IEC 61937-2 (Burst-info). NRF24Z1 is transparent to the specific audio compression algorithms used, it just transfers what comes in on the input side to the receiver side. Except that only the 32 first bits of channel status information bits are transferred, and no user data bits. * Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 26 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Only one of the audio interfaces can be active at one time. The active audio interface for ATX is chosen by bit 2 in register TXMOD (0= I2S is default, see Table 7-16), and for ARX by bit 2 in register RXMOD. 7.5 Audio interface functionality The functionality and direction of the pins in the audio interfaces are listed in Table 7-3. NRF24Z1 Audio interfaces Pin # 9 10 11 12 13 14 MODE=0 (ARX) TXMOD[2]=0 (I2S) Function REQ CLK WS DATA X RESET* MCLK Direction IN OUT OUT OUT IN OUT OUT MODE =1 (ATX) TXMOD[2]=0 (I2S) Function REQ CLK WS DATA X RESET* MCLK Direction OUT IN IN IN IN OUT OUT TXMOD[2]=1 (S/PDIF) Function X X X X SPDIO X Direction IN IN IN IN OUT OUT TXMOD[2]=1 (S/PDIF) Function X X X X SPDIO X Direction OUT IN IN IN IN OUT Pin name REQ CLK WS DATA SPDIO MCLK Table 7-3 Audio interface pin functions * If S/PDIF is not used for audio, the SPDIO pin can be used as RESET (output) to external devices. Please see chapter 10 for further details. 7.5.1 ATX audio interface control The NRF24Z1 in ATX mode automatically detects the rate of a digital audio stream from an external master both on the I2S and S/PDIF interface. Register 0x01 holds the status of this detection for optional read back to an external MCU. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 27 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register Hex 0x01 TXSTA R/W R Initial Description Hex 0x40 Audio transmitter status register Bit Interpretation 7 Reserved 6:5 Detected audio scale factor (I2S only) 00 0.25 01 0.5 10 1 11 21 4:3 Detected audio fundamental rate 00 48 kHz 01 44.1 kHz 10 32 kHz 11 Illegal or no input detected 2:0 Audio transmitter state (TBD) Table 7-4 Audio input status Default NRF24Z1 transfers uncompressed audio, but it has some options to transfer companded audio data. This can be used to save power, or to accommodate transfer of 24 bit audio, which uncompanded would exceed the radio bandwidth. This is a lossy compression/decompresion in the way that superfluous LSB's are lost. Here is an example of how 24 to 16 bit compand works: If the sample values within an audio frame are within +/- 200000, 3 LSB are cut, and if sample values of the next frame is within +/- 60000, only 1 LSB is lost. So the number of LSB lost varies dynamically with maximum sample value for each frame, and this limits the relative error. Register Address Hex 0x11 TXFMT R/W R/W Initial Description Hex 0x00 Transmit data format Value 0 1 2 4 Table 7-5 : register TXFMT. Interpretation 16 bit linear PCM 24 bit linear companded to 16 bit Reserved 16 bit linear companded to 8 bit 1 For 2x rate (96 kHz) every second sample is discarded in ATX, and in ARX the remaining samples are output at 1x rate. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 28 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer The Audio interfaces in ATX mode are controlled by registers 0x1A (Bit[4], Bit[2:0]) and 0X14 listed in Table 7-5. Address Register Hex 0x1A TXMOD R/W Initial Description Hex R/W 0x00 Operation modes for audio transmitter 7 RF transmitter enable 6 Audio transmitter power down 5 Enable wakeup on changing DD[1] 4 REQ pin polarity (0 for active low) 3 Enable direct data from pins DD[2:0]. DD[2] is only available if SSEL=1 2 S/PDIF enable (default input is I2S) 1:0 MCLK output control** 00 MCLK off (logic 0) 01 Output 256 x 48 kHz 10 Output 256 x 44.1 kHz 11 Output 256 x 32 kHz R/W 0x00 I2S interface configuration (on ATX side), see also Table 7-2 7 Data enable 0 I2S carries sound 1 I2S carries data 6 Reserved, MBZ 3 WS Polarity 0 WS=0: Left sample (std) 1 WS=1: Left sample 2 Data to Bit Clock relation (data valid at clock edge) 0 Rising Edge (standard) 1 Illegal 1 WS to MSB delay 0 1 clock cycle (standard) 1 0 clock cycles 0 Audio word justification 0 Left justified 1 Right justified 0x14 I2SCNF_IN Table 7-6 ATX audio input control **IMPORTANT NOTE! For S/PDIF audio input, MCLK output is disabled, but the MCLK control value TXMOD[1:0] should generally be set to the expected sampling rate. This is mandatory if 32 kHz sampling rate is expected, and recommended otherwise. Setting MCLK to the expected sampling rate gives the best phase margin and hence sampling quality when the input S/PDIF signal has much jitter. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 29 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer To pace I2S data a REQ output signal is used. Polarity is set in TXMOD[4]. In I2S data mode (I2SCNF_IN7=1) I2S DATA and CLK input must be stopped within 32 CLK cycles when REQ goes inactive, and must start again when REQ goes active. For analog audio sources, the NRF24Z1 offers a 256x clock output on pin MCLK (TXMOD[1:0]). This clock can be used as system clock for an external stereo ADC. If I2S is used for data transfers (I2SCNF_IN[7] = 1), average data rate is set in register 0x15 Address Register Hex 0x15 I2SRAT R/W Initial Description Hex R/W 0x00 I2S interface speed for digital input streams that are not interpreted as audio by NRF24Z1. n (dec) Digital stream 0 8 kbit/s 1 16 kbit/s 2-190 (n+1)*8 kbit/s 191 1536kbit/s >191 Illegal Table 7-7 ATX I2S data transfer control 7.5.2 ARX audio interface control In ARX mode the audio interfaces are controlled by the registers 0x4A and 0x44 listed in Table 7-8. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 30 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register Hex 0x4A RXMOD 0x44 I2SCNF_OUT R/W Initial Description Hex R/W 0x00 Set operation modes for audio receiver Bit Interpretation 7 Receiver power down 6 Reserved, MBZ 5 RF receiver enable 4 REQ pin polarity 3 Reserved, MBZ 2 S/PDIF enable 1:0 Reserved, MBZ R/W 0x00 I2S interface configuration for audio output (on ARX side), see also Table 7-2 Bit Interpretation 7 Reserved, MBZ 6 Mute sound output 5:4 Sample length 00 16-bit samples 01 reserved 10 24-bit samples 11 reserved 3 WS Polarity 0 WS=0: Left sample (std) 1 WS=1: Left sample 2 Data to Bit Clock relation (data valid at clock edge) 0 Rising edge (standard) 1 Falling edge 1 WS to MSB delay 0 1 clock cycle (standard) 1 0 clock cycles 0 Audio word justification 0 Left justified 1 Right justified Table 7-8 ARX audio interface control registers In I2S data mode (I2SCNF_IN7=1) I2S DATA and CLK out will be stopped within 32 CLK cycles when REQ input goes inactive, and will start again when REQ goes active. NOTE: After reset, the ARX registers can be accessed by the audio transmitter (NRF24Z1 in ATX mode) through the control and data channel set up between two linked NRF24Z1. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 31 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7.5.3 I2S Audio interface timing I2S input (ATX) timing The I2S input protocol is configurable to handle several I2S formats. In addition, the interface will automatically detect sample size and word length for the most common formats. This section shows the detailed bit, clock and word timing requirements. TI2S >= 0.35TI2S >= 0.35TI2S CLK tsI2S thI2S VH = 2.0V VL = 0.8V DATA and WS TI2S = clock period thI2S = hold time I2S receiver tsI2S = setup time I2S receiver Figure 7-2. Timing for I2S input on NRF24Z1, for values see Table 13-1 I2S output (ARX) timing I2S output is protocol compatible with most I2S DACs and CODECs. TI2S >= 0.35TI2S >= 0.35TI2S CLK tdI2S VH = 2.0V VL = 0.8V DATA and WS TI2S = clock perod tdI2S = delay I2S transmitter Figure 7-3. Timing for I2S output of NRF24Z1, for values see Table 13-1 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 32 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7.6 Serial master interfaces The NRF24Z1 serial master interfaces group contains a SPI and a 2-wire master interface available at all times. After RESET the NRF24Z1 will look for a serial memory on the SPI master interface. If no memory is present, the process is repeated on the 2-wire interface. If no memories is found an NRF24Z1 assumes an external microcontroller will configure it over one of the slave control interfaces and will hence be idle until that happens. Link initialization will start as soon as the necessary control register bits are set. During the configuration the SPI master is operated at 1MHz or 0.5MHz. SPI format is CPOL=0, CHPA=0 as used by industry standard EEPROM/FLASH memories. The NRF24Z1 is protocol compatible with SPI memory with sizes ranging from 1 Kbyte to 64 Kbytes with 16-bit sub-address used. The slave(s) that are connected determines the protocol on the 2-wire master interface. For the case of configuration, NRF24Z1 is protocol compatible with "industry standard" 2-wire memory with sizes ranging from 128 bytes to 4 Kbytes (with 3 address pins and one byte sub-address used). During configuration this interface is operated at 100 kHz for compatibility with most serial 2-wire memories. The pin out and functionality of the serial master I/O pins are shown in Table 7-9. NRF24Z1 I/O: serial masters ARX mode MODE=0 RXDCMD[7] = 0 Functio n MSDA MSCL X X X RESET * X ATX mode MODE=1 and EEPROM connected to SPI Function X RESET* X MSCN MMISO Direction IN OUT IN OUT IN MODE=0 RXDCMD[7] = 1 MODE =1 and EEPROM connected to 2 wire Function MSDA MSCL X X X RESET* X Direction IN/OUT OUT IN IN IN OUT IN pi n 27 28 29 30 name MSDA MSCL MSCN MMISO Direction IN/OUT OUT IN IN IN OUT IN Function X RESET* X MSCN MMISO Direction IN OUT IN OUT IN 31 35 MMOSI MSCK MMOSI MSCK OUT OUT MMOSI MSCK OUT OUT Table 7-9 Serial masters functionality * A pin in the serial interface that is NOT used for external memory and/or controlling external circuitry can be configured to act as reset for external devices such an ADC or DAC. Please refer to chapter 10 for further details. After configuration, the master interfaces in ATX go idle with pins still active, while the interfaces in ARX become an extended arm of a linked ATX through the control channel between two NRF24Z1. The set-up of the serial master interfaces of the ARX after configuration is loaded is controlled by register RXDCMD (0x70) as shown in Table 7-10. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 33 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register Hex 0x70 RXDCMD R/W Initial Description Hex R/W 0x82 Data "command". Specifies interface and speed Bit Interpretation 7 Interface select 0 Use ARX 2-wire interface 1 Use ARX SPI interface 6:4 SPI slave select control. Set which signal to be used as slave select, and associated polarity. Or 2-wire access type. Value SPI interpretation 000 CSN, active low 2 001 DO[0], active low 1 010 DO[1], active low 1 011 DO[2], active low 1 100 CSN, active low 2 101 DO[0], active high1 110 DO[1], active high1 111 DO[2], active high1 Value 2-wire interpretation 000 start stop access 001 start only access (a start only access followed by a start-stop access will be a start-start-stop access) Notes: 1. In order to use any of DO[2:0] as SPI slave selects, the corresponding bit in RXPIO should be set to the SPI slave select inactive state. I.e. if DO[0] is to be used as active low slave select, RXPIO[0] must be set to 1. MCSN is always active low 2. 3:1 0 Table 7-10 RXDCMD register Speed select Value SPI (bin) Interpretation 000 8 Mbit/s 001 8 Mbit/s 010 4 Mbit/s 011 2 Mbit/s 100 1 Mbit/s 101 500 kbit/s 110 250 kbit/s 111 Reserved Reserved, MBZ. 2-wire Interpretation Illegal 100 kbit/s 400 kbit/s 1 Mbit/s Illegal Illegal Illegal Reserved Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 34 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Number of bytes data to read/write is set in `write and read count' registers RXWCNT (0x71) and RXRCNT (0x72) and the actual data are transferred through the data buffers RXWBUF and RXRBUF. Once the above registers are set, writing to RXEXEC will initiate a SPI or 2-wire operation on the ARX serial master interfaces. Operation finished is also reported in RXEXEC and can be coupled to an interrupt in the ATX. See also Figure 5-2 NRF24Z1 control and data link Remember that all interaction with these registers is done through the slave interfaces on the ATX. The data in RXWBUF are transferred to the ARX via RF and the interactions are carried out on the ARX side as configured in RXDCMD. Once it is completed and data read by the ARX is transferred back to the ATX, the `operation finished' interrupt (flag INTSTA.4) is set and data read on the ARX side are available in RXRBUF. Address Hex 0x71 0x72 0x500x5f 0x600x6f 0x74 Register RXWCNT RXRCNT RXWBUF RXRBUF RXEXEC R/W Initial Hex R/W 0x00 R/W 0x00 W 0x00 R W/R 0x00 0x00 Description Number of bytes to write (max 16) Number of bytes to read (max 16) Data to be written to the interface specified by RXDCMD Data read from audio receiver on the interface specified by RXDCMD Write to this register will execute a command on the audio receiver. The interface and speed are specified by RXDCMD. The audio receiver will first write RXWCNT bytes from RXWBUF to the selected interface, then read RXRCNT bytes and transmit back to be stored in RXRBUF. An interrupt may be delivered upon successful completion of the command. 0= idle; 1=write or read MCU must set RXEXEC=1 to perform command, and can thereafter read RXEXEC to find if command is finished (idle) Table 7-11 ARX master data registers Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 35 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7.6.1 Timing serial master interfaces SPI master timing tdMSCK T MSCK MCSN MSCK tdMSPI MMOSI MSB LSB tsuMSPI MMISO MSB thdMSPI LSB Figure 7-4 : SPI master interface timing, here is shown a one byte transaction. TMSCK : MSCK cycle time, as defined by RXDCMD register. tdMSCK : time from MCSN active to first SCK pulse, tdSCK = TMSCK / 2 tdMSPI : delay from negedge MSCK to new MMOSI output data tsuMSPI : MMISO setup time to posedge MSCK. thdMSPI : MMISO hold time to posedge MSCK. for values see Table 13-1 2-wire master timing START Condition STOP Condition SDA SCL 1-7 ADDRESS R/W 8 9 ACK 1-7 DATA 8 9 ACK 1-7 DATA 8 9 ACK Figure 7-5 : 2-wire data transfer Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 36 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer TMSCL MSCL tMW2_od tMW2_od MSDA out MSDA in tMW2_dsu tMW2_dhd Figure 7-6 : 2-wire master timing, for values see Table 13-1 7.7 Control and GPIO interfaces The following control and GPIO interfaces are found: * * ATX: SPI or 2-wire slave interfaces and general purpose inputs(DD [2:0]) ARX: SPI or 2-wire slave interfaces as for ATX, or GPIO pins DI[3:0], DO[3:0] with alternative functionality: PWM or master SPI chip select signals The ATX serial slave interfaces are the main channel for external applications or devices to control the NRF24Z1 and the RF communication. All register access and all but the most basic control and data transfers' takes place through one of these interfaces. If an external controlling device (microcontroller) is not present in the audio transmitter (ATX), NRF24Z1 configuration can only be done once directly after RESET (section 7.6). All audio and RF link set-up is fixed and the data/control channel offered can only carry simple button push/interrupt signals. 7.7.1 ATX control and GPIO pins In ATX mode the pins are mainly carrying the serial slave control interfaces that enables access and control of all the NRF24Z1 registers both in the device physically connected and a linked ARX (through the NRF24Z1 data/control RF channel). One of two interfaces can be chosen based on the level of input pin SSEL. SSEL = 0; SPI (pins SCSN, SSCK, SMISO, SMOSI). SSEL = 1; 2-wire (pins SADR, SSCL and SSDA) The functionality and signal direction of the pins in ATX mode are listed in the table below. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 37 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer NRF24Z1 GPIO and serial slave interface pins ATX mode Device control: SPI MODE, SSEL = 10 Device control: 2-wire MODE, SSEL =11 Function SSEL SSDA SSCL SADR DD[2] DD[1] DD[0] MODE IRQ pin 1 2 3 4 6 7 8 26 36 name Function SSEL SMISO/SSDA SSCK/SSCL SCSN/SADR SMOSI/DD[2] DD[1] DD[0] MODE IRQ SSEL SMISO SSCK SCSN SMOSI DD[1] DD[0] MODE IRQ Direction IN OUT IN IN IN IN IN IN OUT Direction IN IN/OUT IN/OUT IN IN IN IN IN OUT Table 7-12 ATX Control and GPIO pins functionality 7.7.2 SPI slave interface The first byte of the SPI transaction is a special command which specifies the register address and whether it is a read or a write access. The seven least significant bits in the first byte is the NRF24Z1 register address, while the most significant bit is the read/write indicator (read=1,write=0), see Table 7-13 B7 R/W B6 B5 B4 B3 B2 B1 Register address B0 Table 7-13 SPI command byte encoding Write transaction : The next byte on SMOSI will be put into register with address as set in the first byte. Writing more bytes will autoincrement the register address. Read transaction : The next byte on SMISO will be value of register with address as set in first byte. Reading more bytes will autoincrement the register address. Consecutive accesses with SCSN low will auto-increment the address. This means that all registers may theoretically be accessed with one SPI transfer. 7.7.3 2-wire slave interface This interface is similar to what is found on serial memories and data converter devices. The 7-bit device address of NRF24Z1 is `a101001', where `a' is the logic level of the SADR input pin (read during power up and reset only). Each 2-wire transaction is started with the "Start condition" followed by the first byte which contains the 7 bit long device address and one read/write bit, this byte is hereafter referred to as the "address/read command byte" or the "address/write command byte" depending on the state of the read/write bit, read=1, write=0. The second byte contains the Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 38 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer register address which specifies which NRF24Z1 register is to be accessed. This address will be written into the ATX chip, it is therefore necessary that the first byte after the first start condition is an address/write command. Further actions on the 2-wire interface depend on whether the access is a read or write access. W2 command byte is illustrated in Table 7-14. B7 a B6 1 B5 0 B4 1 B3 0 B2 0 B1 1 B0 R/W Table 7-14 : 2-wire command byte encoding 7.7.3.1 2-Wire write access. Figure 7-7 illustrates a simple write operation, where one byte is written to the ATX chip. Stop Device Address (7-bit) Register address Data IN Start Write ACK ACK ACK Figure 7-7 : example of a 2-wire write operation A write access is composed by a start condition, an address/write command byte, a register address byte and a data byte which will be written to the register specified in the previous register address byte. Each byte will be acknowledged by the 2-wire slave by pulling the data line (SDA) low. To stop the write access a stop condition should be applied on the 2wire interface. See Figure 7-9 for an example. Consecutive write access is performed by postponing the stop condition. 7.7.3.2 2-Wire read access Figure 7-8 illustrates a simple read operation, where one byte is read back from the ATX chip. NACK Device Address (7-bit) Register address Device Address (7-bit) Data IN Start Write ACK ACK Start (repeated) Read ACK Stop Figure 7-8 : example of a 2-wire read operation A read access is composed by a start condition, an address/write command byte, and a register address byte. These two bytes are acknowledged by the 2-wire slave. This scenario is followed by a repeated start condition and an address/read control byte. This byte is also Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 39 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer acknowledged by the 2-wire slave. After the acknowledge bit has been sent from the 2-wire slave, the register value which corresponds to the register address byte will be supplied by the 2-wire slave as well. This byte should be acknowledged by the 2-wire master if consecutive register read is wanted. The read access is stopped by not acknowledging the last byte read, followed by a stop condition. See Figure 7-9 for an example. Start condition 1 D7 Stop condition 8 D0 9 ACK 1 D7 8 D0 9 ACK/NACK Figure 7-9 : example of 2-wire waveform 7.7.4 General purpose input pins D[2:0] Three (2 if SPI slave is used, SSEL=0) general purpose inputs are also available. The status on these pins can be read in register 0x20 Address Register Hex 0x20 TXDD R/W R Initial Description Hex 0x00 Value of ATX DD input pins Bit Interpretation 7:3 Reserved, do not use 2 Value of DD2 (only if SSEL=1) 1 Value of DD1 0 Value of DD0 Table 7-15 ATX DD[2:0] status If bit TXMOD[3] is set the levels of pins DD[2:0] are mirrored on pins DO[2:0] on a linked ARX device directly. See Table 7-16 Address Register Hex 0x1A TXMOD R/W R/W Initial Description Hex 0x00 Operation modes for audio transmitter 7 RF transmitter enable 6 Audio transmitter power down 5 Enable wakeup on changing DD[1] 4 REQ pin polarity 3 Enable direct data from pins DD[2:0]. DD[2] is only available if SSEL=1 2 S/PDIF enable 1:0 MCLK output control Table 7-16 TXMOD register Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 40 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer The IRQ pin can act as an interrupt signal to the outside application. There are a number of interrupt sources available; this is described further in chapter 9. 7.7.5 ATX Control interface timing 7.7.5.1 SPI slave timing The SPI slave can operate with up to 8 MHz clock speed over the full operation range of the device. With a 3V +/-10% supply the maximum clock speed is 16MHz. However note that there is a minimum pause interval tSRD between writing or reading a each byte. tdSSCK TSSCK tSRD SCSN SSCK tdSSPI SMISO MSB LSB tsuSSPI thdSSPI LSB MSB next byte SMOSI MSB MSB next byte Figure 7-10 : SPI slave timing diagram TSSCK : SSCK cycle time. tdSSCK : time from SCSN active to first SSCK pulse tdSSPI : delay from negedge SSCK to new SMISO output data tsuSSPI : SMOSI setup time to posedge SSCK thdSSPI : SMOSI hold time to posedge SSCK tSRD : minimum pause between each byte read from or written to slave SPI for values see Table 13-1 7.7.5.2 2-wire slave timing The interface supports 100 kHz, 400 kHz and 1MHz over the operating range of the device. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 41 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer T SSCL SSCL tSW2_dsu tSW2_dhd SSDA in SSDA out tSW2_od tSW2_od Figure 7-11 : 2-wire slave timing diagram, for values see Table 13-1 7.7.6 ARX control interface options ARX is default configured with a control slave interface, identical to ATX slave interface, SPI or 2-wire as selected by pin SSEL, in the same way as for ATX. The slave interface gives local access to all registers in ARX, but not to any registers on the ATX side. Alternatively if bit 6 of RXSTA register is set in the configuration EEPROM, ARX will be configured with GPIO pins instead of slave control interface pins. The pin out and functionality of the slave interface or GPIO pins are shown in Table 7-18 Address Hex 0x06 Register RXSTA R/W R Initial Hex 0x00 Description ARX status register. Bit 7 6 Interpretation RXEXEC status, 1 is OK, 0 is error 0 : ARX has control slave interface 1 : ARX has GPIO interface, which implies no control slave interface Table 7-17: ARX status register Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 42 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer ARX with SPI slave interface RXSTA6 = 0, SSEL=0 Pin Function Direction ARX with 2-wire slave interface RXSTA6 = 0, SSEL=1 Function Direction ARX with GPIO interface RXSTA6 =1 Function Direction 1 2 3 4 6 36 SSEL SMISO SSCK SCSN SMOSI IRQ1 IN OUT IN IN IN OUT SSEL SSDA SSCL SADR DI2 IRQ IN IN/OUT IN/OUT IN IN OUT DO2 DO1 DO0 DI3 DI2 DO3/PWM2 OUT OUT OUT IN IN OUT Table 7-18: ARX slave interface or GPIO pins. Note that the GPIO functions described for registers RXPIO, RXPWME, RXPWMD, RXPIN bits 3:2, RXWAKE bits 3:2, are only alvailable if ARX is configured with GPIO interface (RXSTA6=1). However these registers may always be read or written to, but if ARX is configured with slave interface, the registers will be disconneted from their corresponding GPIO pins. Note also that if ARX is configured with slave interface, many ARX registers can be accessed both over the air from ATX, and locally via slave interface, and it is the sole responsibility of the external MCU's to avoid setting conflicting values to a register. 7.7.7 ARX GPIO pins ARX mode has general purpose inputs DI[3:0] and outputs DO[3:0]. OUTPUTS General purpose pins DO[3:0] can be controlled in several ways: Pins DO[3:0] DO[2:0] DO[2:0] DO[3] Functionality General purpose output Mirror of DD[2:0] ARX SPI master bus enable PWM output Controlling register RXPIO (0x41) TXMOD (0x1A) RXDCMD (0x70) RXPWME (0x42) RXPWMD (0x43) Description See below Section 7.7.1 Table 7-10, Section 7.6 See below Table 7-19 DO[3:0] alternate functions 1 In ARX slave mode, there is only one interrupt event, which is "wakeup from powerdown" flag, bit 2 of INTSTA register. ATX and ARX has each its own local instance of the INTSTA register. 2 General purpose output (DO[3]) or PWM functionality set in register RXPWME (0x42) Phone +4772898900 Fax +4772898989 April 2005 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Page 43 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Used as general purpose outputs DO[3:0] are controlled by register RXPIO (0x41). On all general purpose outputs of the ARX, high current drive capabilities can be enabled to drive LED's for instance. The register content of 0x41 is given in Table 7-20. Address Register Hex 0x41 RXPIO R/W Initial Description Hex R/W 0x00 Receiver GPIO output and drive strength Bit 7 6 5 4 3 2 1 0 Table 7-20 Register 0x41 RXPIO Pin DO[3] can also be used as a PWM output. PWM enable and PWM frequency is controlled by register RXPWME (0x42) while PWM duty cycle is controlled by register RXPWMD (0x43) as shown in Table 7-21. Logic 1 Interpretation High drive high enable for DO[3] High drive low enable for DO[2] High drive high enable for DO[1] High drive low enable for DO[0] Data for DO[3] Data for DO[2] Data for DO[1] Data for DO[0] Register Address Hex 0x42 RXPWME R/W Initial Description Hex R/W 0x00 Enables audio receiver PWM onto DO[3] and set PWM frequency Bit Interpretation 7:6 00 : PWM not enabled 11 : Enable PWM on DO[3] 01,10 : reserved, do not use 5:0 PWM frequency (repetition rate) fPWM=16MHz/(255*(1+RXPWME[5:0])) Set audio receiver PWM duty cycle 0x43 RXPWMD R/W 0x00 Table 7-21 Registers RXPWME (0x42) and RXPWMD (0x43) Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 44 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer INPUTS DI[3:0] are in ARX general purpose inputs. The status on these pins is monitored in register RXPIN (0x07). Address Register Hex 0x07 RXPIN R/W Initial Description Hex R 0x00 Current state of audio receiver GPIO inputs Bit 7:4 3 2 1 0 Table 7-22 Register RXPIN (0x07) Interpretation Reserved, do not use. DI3 value DI2 value DI1 value DI0 value 7.8 Data Channel Timing 7.8.1 Forward data channel, data transfer from ATX to ARX Data communication from ATX to ARX is performed through a dedicated data channel which is superimposed on the audio stream. Maximum data rate on this channel can be calculated with formula 1 and formula 2. BRR = AFR/(8*16) DR = BRR*NPB*NBP*8bits BRR: AFR: DR: NPB: NBP: frame/sec bits/sec (1) (2) Frame Repetition Rate, time interval between start of data frames. Audio Fundamental Rate (sampling frequency). Average Data Rate on data channel. Number of Packets per Frame. Number of data Bytes per Packet. NRF24Z1 has the following parameters for the ATX to ARX data channel: AFR: 48 kHz, 44.1 kHz or 32 kHz NPB: 4 NBP: 1 Table 7-23 lists resulting data rates. Fundamental rate of audio signal 48kHz 44.1kHz 32 kHz Table 7-23 : forward data channel rate Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Maximum data rate on data channel 12000 bits/sec 11025 bits/sec 8000 bits/sec Page 45 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7.8.1.1 Limitations in forward data channel, effective data rate. The data rate shown in Table 7-23 is shared by the different inputs. Data from all interfaces are fed into a FIFO queue, so that high activity on one source will increase the link delay for the other sources. Effective data rate on forward data channel depends mainly on the link quality, a poor link can reduce data rate. 7.8.2 Return data channel, data transfer from ARX to ATX Data communication from ARX to ATX is performed through a dedicated data channel which is built into the acknowledge data stream. Maximum data rate on this data channel can be calculated with Formula 1 and Formula 2 with NPB = 1 and NBP = 5, see Table 7-24. Fundamental rate of audio signal 48kHz 44.1kHz 32 kHz Table 7-24 : return data channel rate 7.8.2.1 Limitations in return data channel Data transfer from ARX to ATX can be divided into three groups: 1. Link quality monitoring. 2. Parallel port monitoring. 3. ARX master interface communication. These three groups shares the same bandwidth of the return channel. As can be seen in the following sections, each function is assigned a fraction of return channel data rate shown in Table 7-24. 7.8.2.2 Link quality monitoring Refresh rate of link quality register, LNKQ depends on the data rate shown in Table 7-25. This feature requires 20% of the total band-width of the return data channel. Fundamental rate of audio signal 48kHz 44.1kHz 32 kHz Table 7-25 :LNKQ data rate LNKQ data rate on return data channel 3000 bits/sec 2756 bits/sec 2000 bits/sec Maximum data rate on return data channel 15000 bits/sec 13781 bits/sec 10000 bits/sec Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 46 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 7.8.2.3 Parallel port monitoring The parallel port is updated according to the data rate shown in Table 7-26. This requires 10% of the total band-width of the return data channel. Fundamental rate of audio signal 48kHz 44.1kHz 32 kHz Table 7-26 : Parallel port data rate 7.8.2.4 Master interface communication Parallel port data rate on return data channel 1500 bits/sec 1378 bits/sec 1000 bits/sec Effective data rate of master interface communication when transferring data from ARX to ATX can be seen in Table 7-27. This requires 50% of the total band-width of the return data channel, 20% for data and 30% for synchronization and address overhead. Fundamental rate of audio signal 48kHz 44.1kHz 32 kHz Table 7-27 : serial master interface data rate Master interface data rate on return data channel 3000 bits/sec 2756 bits/sec 2000 bits/sec 20% of the total band-width of the return data channel is spare for future use. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 47 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 8 QUALITY OF SERVICE (QOS) AND RF 8.1 Link algorithm The link algorithm of the nRF2Z1 is fully managed on-chip. Time spent searching for counterparts can be controlled by the power down counters presented in chapter 11. 8.2 RF protocol The RF protocol of NRF24Z1 is fully controlled on-chip, the only parameter configurable by the end system is the address length and address to be used in the RF protocol. This enables numerous NRF24Z1 to be identified and accessed independently in the same physical area. The RF protocol address length and address are set in registers ALEN and ADDR, listed in Table 8-1. Address Hex 0x38 0x39 0x3A 0x3B 0x3C 0x3D Register ALEN ADDR[0] ADDR[1] ADDR[2] ADDR[3] ADDR[4] R/W R/W R/W R/W R/W R/W R/W Initial Hex 0x05 0x01 0x02 0x03 0x04 0x05 Description Address length in bytes, legal range is 4 or 5 Address byte #0 (LSB) Address byte #1 Address byte #2 Address byte #3 Address byte #4 (don't care if ALEN =4) Table 8-1 RF protocol address 8.3 Adaptive frequency hopping NRF24Z1 features adaptive frequency hopping. This enables the NRF24Z1 link to handle RF reflections, multi-path fading and avoid heavily trafficked areas of the 2.4 GHz band. This enables stable operation both in challenging environments physically and in coexistence with other 2.4 GHz systems. The fundamental channel hopping algorithm is based on three parameters. These are lowest channel to be used, highest channel to be used and channel step between transactions on the air. These parameters are set in registers CHP1, CHP2 and CHP3. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 48 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register Hex 0x35 CHP1 R/W R/W 0x36 CHP2 R/W 0x37 CHP3 R/W Initial Description Hex 0x01 CHP1 is minimum channel number to be used by the channel hopping routine. For optimal performance set to: 0x01 0x13 CHP2 is maximum channel number to be used by the channel hopping routine.For optimal performance set to: 0x13 0x05 The number of channels the frequency hopping routine is to move before next transaction on the air. Recommended values: 0x04, 0x05, 0x06, 0x07, 0x08, 0x09 Table 8-2 Frequency hopping set-up The frequency hopping algorithm uses the registers above as follows: PCh = PCh + CHP3 if (PCh > CHP2) PCh = PCh - (CHP2 - CHP1 + 1) Where: PCh : Present Channel As can be seen from the equation above the frequency hopping routine is a wrap around routine. If CHP3 is not set well the wrap around may lead to only a fraction of the available channels to actually be used. By using one of the recommended CHP3 values in Table 8-2, one gets maximum utilisation of the 2.4 GHz band and best co-existence between multiple NRF24Z1 systems. The available channels and the corresponding centre frequencies are listed in Table 8-3 . Channel number 1 2 3 4 5 6 7 8 9 10 Frequency (MHz) 2404 2408 2412 2416 2420 2424 2428 2432 2436 2440 Channel number 11 12 13 14 15 16 17 18 19 Frequency (MHz) 2444 2448 2452 2456 2560 2464 2468 2472 2476 Table 8-3 : RF channel centre frequencies Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 49 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 8.3.1 Adapting to the RF environment In a clean RF environment, which means few or no other RF transmitters nearby, the NRF24Z1 set up like recommended in Table 8-2 will use all the channels in Table 8-3. If another RF system appears in the same area, the NRF24Z1 system is likely to collide with the other system on some of the channels and loose one or more RF packets. If the poor quality on a certain channel prevails, ATX removes it from the channels used by the frequency hopping algorithm. A synchronized frequency hopping table is kept in the ARX by use of the service channel superimposed on the audio stream. The communication problems on this channel will hence not affect the NRF24Z1 link quality thereafter. The channels that are taken out of the channel hopping sequence are put on a five level FIFO list. The first channel in the list will hence be released when the sixth channel with too poor communication quality is found. With this list the NRF24Z1 can in all refrain from using 20 MHz of the 2.4 GHz band which means that it is capable of masking out an entire WLAN channel for instance. To minimise linking time between two NRF24Z1, the same basic frequency hopping scheme (CHP1-CHP3) must be set on both ATX and ARX side. 8.4 Link registers The QoS engine by use of the input from the registers presented above will maintain a RF link. The NRF24Z1 has a number of link registers which primary function is to monitor the overall quality on the link and enable actions to be taken based on it. The link monitoring registers are listed in Table 8-4.. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 50 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register Hex 0x04 LNKQ R/W R 0x05 LNKERR R 0x31 LNKWTH R/W 0x32 LNKETH R/W Initial Description Hex 0x00 Link quality register. Number of successfully transferred packets per unit of time. A value of 0 means all packets out of 256 are lost, a value of 128 means that 50% of the packets were lost and a value of 255 means that no packet out of 256 is lost. This number always represents the status over the last 256 packets transmitted. 0x00 Link error register. Number of audio packets permanently lost per unit of time. A packet is permanently lost if it's not successfully received at the time its required at the audio output. A permanently lost will be audible! 0xff Link warning threshold limit. A LNKQ value <= LNKWTH will cause IRQ to be activated (if enabled by INTCF.5) 0xff Link error threshold limit. A LNKERR value >= LNKETH will cause IRQ to be activated (if enabled by INTCF.5) Table 8-4 Link quality monitoring registers Registers LNKQ shows how hard the quality of service engine is working to maintain the link and the LNKERR shows how many times it has actually failed. LNKWTH and LNKETH enable the main system to be interrupted if one or the other of these quality indicators drops below an acceptable level. The overall status of the link can be monitored in register LNKSTA and direct actions to be taken upon the quality requirements set in LNKWTH and LNKETH can be set in register LNKMOD. Registers LNKSTA and LNKMOD are listed in Table 8-5. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 51 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register Hex 0x03 LNKSTA R/W R Initial Description Hex 0x00 Link status register Bit Interpretation 7:6 Reserved, do not use 5 LNKERR Changed 4 LNKQ Changed 3:1 Reserved, do not use 0 Link established Link mode register. Bit 7 6 Interpretation Reserved ATX and ARX will reset to initial register content if no counterpart is found on next link initialization. Reserved, MBZ Reserved, MBZ. Action when LNKERR > LNKETH Value Interpretation 00 Mute 01 Reserved, MBZ 10 Reserved, MBZ 11 No action Action when LNKQ < LNKWTH Value 00 01 10 11 Interpretation Mute Reserved, MBZ Reserved, MBZ No action 0x30 LNKMOD R/W 0x00 5 4 3:2 1:0 Table 8-5 Link registers 8.4.1 RF link latency It is possible to trade link robustness versus link latency. In systems where latency is not important, like CD player headsets, high latency option should be used. Latency is set in TXLAT register as shown below. Note that delay depends on audio sampling rate Fs. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 52 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Address Register R/W Initial Description Hex Hex 0x12 TXLAT R/W 0x00 ATX to ARX Latency Value Interpretation Fs = 48kHz 0 Nominal 12.5ms 1 High 20 ms 2 Short 7 ms Table 8-6 Register TXLAT 8.5 RF output power Fs= 44.1kHz 13 ms 21.5ms 7 ms Fs= 32kHz 16 ms 28 8 ms The only configurable parameter in the RF sub system are the RF output power from the device. The output power are set in registers TXPWR for ATX and RXPWR for ARX. Address Register Hex 0x16 TXPWR R/W Initial Description Hex R/W 0x03 Audio transmitter output power Value Interpretation 0 -20 dBm 1 -10 dBm 2 -5 dBm 3 0 dBm R/W 0x00 Audio receiver output power Value Interpretation 0 -20 dBm 1 -10 dBm 2 -5 dBm 3 0 dBm 0x49 RXPWR Table 8-7 Registers TXPWR and RXPWR Note that both the output power registers are accessible from the ATX an external system may hence tune the output power based on the result of the RF link quality registers presented above. Reducing the output power from a RF device both saves current and eases the co-existence with this device. Remember that the other RF system your system are colliding with may well be another (of your) NRF24Z1 systems. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 53 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 9 INTERRUPTS A NRF24Z1 in ATX mode can deliver a interrupt to the external system on pin IRQ. Interrupt sources are set in register INTCF (0x13) and interrupt status flags are available in register INTSTA (0x02) . Address Register R/W Initial Description Hex Hex 0x02 INTSTA R 0x00 Read interrupt status. Clear interrupt source bits that are read out. Bit Interpretation 7 Reserved, do not use 6 link broken status flag 5 poor link quality status flag 4 remote transfer done status flag 3 remote input changed status flag 2:0 Reserved, do not use See INTCF for interrupt enabling 0x13 INTCF R/W 0x00 Interrupt configuration. Select events that can generate interrupt on the IRQ pin. Bit 7 6 5 4 3 2:0 Table 9-1 Registers INTCF and INTSTA Interpretation Interrupt polarity, 1 is active high Enable link broken interrupt Enable poor link quality interrupt Enable remote transfer done interrupt Enable remote input changed interrupt Reserved, MBZ Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 54 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 10 RESET OUTPUTS Some pins of the NRF24Z1 not used for other functionality can provide reset pulses to external peripherals. The need for external RESET's happens when NRF24Z1 is operated standalone and no `intelligent' devices such as a microcontroller are available to provide RESET to peripherals (such as ADC or DAC). This external RESET is will happen after configuration data is loaded into NRF24Z1 and RESET level will be kept until NRF24Z1 is ready to stream data. Which NRF24Z1 I/O pin to use and polarity of the reset signal is controlled by registers TXRESO (0x10) for ATX and RXRESO (0x40) for ARX peripherals. The registers are described in the table below. Address Register Hex 0x10 TXRESO R/W Initial Description Hex R/W 0x00 Optional RESET pulse output from ATX may be enabled. Bit Interpretation 7:3 Reserved, MBZ 2:1 0 : no RESET output 1 : RESET output on MSDA pin 2 : RESET output on MOSI pin 3 : RESET output on SPDIO pin 0 ATX RESET output polarity 0 : active low 1 : active high length of reset pulse is ca 285us R/W 0x00 Optional RESET pulse output from ARX may be enabled. Bit Interpretation 7:3 Reserved, MBZ 2:1 0 : no RESET output 1 : RESET output on MSDA pin 2 : RESET output on MOSI pin 3 : RESET output on SPDIO pin 0 ARX RESET output polarity 0 : active low 1 : active high length of reset pulse is ca 285us 0x40 RXRESO Table 10-1 TXRESO and RXRESO registers Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 55 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 11 POWER DOWN CONTROL The NRF24Z1 power down mode enables NRF24Z1 applications to set up a number of power saving routines. 11.1 Enter power down NRF24Z1 can only enter power-down mode of the NRF24Z1 if an external controlling device sets it to. The normal way to initiate power down is for a controlling device connected to an ATX to set the linked ARX in power down (register RXMOD[7]=0) and then set the ATX in power down(register TXMOD[6]=0). The registers are shown in Table 11-1. Address Register Hex 0x1A TXMOD R/W Initial Description Hex R/W 0x00 Operation modes for audio transmitter 7 RF transmitter enable 6 Audio transmitter power down 5 Enable wakeup on changing DD[1] 4 REQ pin polarity (0 for active low) 3 Direct data from pins DD[2:0]. 2 S/PDIF enable (default input is I2S) 1:0 MCLK output control** R/W 0x80 Set operation modes for audio receiver Bit 7 6 5 4 3 2 1:0 Table 11-1 Power down control registers Interpretation Receiver power down Reserved, MBZ Reserved, MBZ REQ pin polarity Reserved, MBZ S/PDIF enable Reserved, MBZ 0x4A RXMOD 11.2 Wake up from power down To emerge from power down there are two options; change on external pin and timer controlled. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 56 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 11.2.1 External pin change To minimise current consumption the NRF24Z1 can be put in power down until the level on an external pin is changed to initiate wake up and new link initialization. In ATX there is one pin, DD[1], that can enable a wakeup, it is controlled in register TXMOD[5]. In ARX a wake-up can be initiate by a change on any of the input pins DI[3:0] wake-up enable is controlled by register RXWAKE. The external wake up control registers are shown in Table 11-2 Address Register Hex 0x1A TXMOD 0x45 RXWAKE R/W Initial Description Hex R/W 0x00 Operation modes for audio transmitter 7 RF transmitter enable 6 Audio transmitter power down 5 Enable wakeup on changing DD[1] 4 REQ pin polarity (0 for active low) 3 Direct data from pins DD[2:0]. 2 S/PDIF enable (default input is I2S) 1:0 MCLK output control** R/W 0x28 Wakeup sources for audio receiver Bit 7:6 5 4 3 2 1 0 Interpretation Reserved, MBZ Goto powerdown mode on DI3 change Wakeup on sleep timer Wakeup on DI3 change Wakeup on DI2 change Wakeup on DI1 change Wakeup on DI0 change Table 11-2 external wake-up control registers 11.2.2 Timer controlled wake up The NRF24Z1 can also be run in a power saving mode where timers controls occasional wake up of the device to search for counter parts on the air. In this case the average current consumption will be higher than the power down current itself, but NRF24Z1 will be able to re-initialise the RF link without any user interaction. If the NRF24Z1 don't find any counterparts within a certain time interval after the wake-up it can go back to sleep. When the NRF24Z1 enters power down the link is broken so ATX and ARX timing are no longer synchronised, a separate set of timers are hence found in ATX and ARX. The timer wake up sequence is controlled by a 16 bit sleep interval timer (ATX: TXSTI, ARX: RXSTI) and an 8 bit wake interval timer (ATX: TXWTI, ARX: RXWTI). The Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 57 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer content of the sleep timer control registers sets how many 10 ms intervals the NRF24Z1 will sleep before it wakes up and tries to establish a RF link. The wake interval timers correspondingly sets how many 10 ms intervals the NRF24Z1 should attempt to re-link before it goes back to power down. If the two paired NRF24Z1's are on the air at the same time, a link is established and the controlling device (MCU) on the ATX side must reset timers to prevent a return to power down again. The sleep and wake timers are controlled by the registers shown in Table 11-3. Address Register Hex 0x17 TXSTI[0] R/W R/W Initial Description Hex 0x00 Audio transmitter (and link) sleep timer byte #0 TXSTI is a 16-bit number specifying the number of 10 ms (nominal) periods the audio transmitter should sleep between attempting to establish a new link. 0x00 Audio transmitter sleep timer byte #1 0x00 Audio transmitter wake timer. With TXWTI set to 0, the audio transmitter will not go back to power down mode. A number larger than 0 will specify the number of 10ms (nominal) periods before the audio transmitter will reenter power down mode. 0x00 Audio receiver sleep timer byte #0 RXSTI is a 16-bit number specifying the number of 10 ms (nominal) periods the audio receiver should sleep between attempting to establish a new link. Only used if sleep timer is enabled, see bit 4 of RWAKE register. 0x00 Audio receiver sleep timer byte #1 0x00 Audio receiver wake timer. With RXWTI set to 0, the audio receiver will not go back to power down mode. A number larger than 0 will specify the number of 10ms (nominal) periods before the audio receiver will reenter power down mode. 0x18 0x19 TXSTI[1] TXWTI R/W R/W 0x46 RXSTI[0] R/W 0x47 0x48 RXSTI[1] RXWTI R/W R/W Table 11-3 sleep and wake timer registers 11.3 NRF24Z1 power saving example Combining the two power-down control methods described above is of course no problem. Pushing a button on an active speaker (ARX) every time it is to be used, may be too inconvenient for the user. A timer controlled power saving when the speaker is not in use may hence justify the added current consumption compared to a full power down. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 58 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer On the audio source side (ATX), which can be a CD player, on the other hand the user interacts to start a play back anyway. Here wake up on an external pin can be used. Figure 11-1 shows an example of timer controlled power down in ARX combined with power down with wake up on external pin event in ATX. In this example the ATX is shut down completely until a user activates the player while the speakers will seemingly always be on for the user. MCU initiates power-down on ATX ATX wakes up on external pin event. ATX power-up ATX power-down RXSTI RXWTI ARX power-up ARX power-down RXSTI RXWTI MCU disables sleep timers on ARX and the link is up streaming audio MCU initiates power-down on ARX. ARX wakes up from timer ARX resumes power-down from timer. ARX wakes up from timer Figure 11-1 : NRF24Z1 power saving What is actually happening is that the ARX is listening on the air at regular intervals (polling the air) for incoming traffic from the ATX. Once this happens (CD player is turned on) the ARX goes into normal operation. For an end user this will seem like the loud speaker turns itself on upon incoming RF traffic from ATX. But since the ARX is only listening at intervals set by RXSTI, this time will be experienced as a start up delay by the end user. To get a wireless audio link that responds instantaneous RXSTI should hence be set as short as possible, preferably not longer than the start delay of other parts of the system (CD player motor for instance). At the same time the ratio of ARX active time (RXWTI, using 32 mA) and sleep time (RXSTI, using 4 uA) will decide the average current consumption in the loudspeakers when the system is idle. The final numbers to be put in the power down control timers will hence be a trade-off between the start-up time wanted on the link and the average current consumption one can tolerate when in idle. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 59 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 12 REGISTER UPDATE OVER THE DATA LINK The registers TXCSTATE, LNKCSTATE, RXCSTATE can be used by a ATX MCU to update audio receiver control registers via the data link. Write to these registers from a ARX MCU is illegal. Address Register Hex 0x1B TXCSTATE R/W R/W Initial Description Hex 0x00 controls when to send ATX side registers TXFMT, TXLAT, I2SCNF_IN, I2SRAT over the data link to ARX. 0 : the registers are free to be written. 1 : the registers may not be accessed. Setting TXCSTATE=1 tells ATX to send the registers values to ARX, and TXSTATE will be reset to 0 by ATX upon successful transfer to ARX. Then ATX will break link and relink An external MCU should poll this register before accessing these register. 0x00 controls when to send ATX side Link control registers over the data link to ARX. 0 : Link control registers free to be written. 1 : Link control registers may not be accessed Setting LNKCSTATE=1 tells ATX to send Link control registers values to ARX, and LNKCSTATE will be reset to 0 by ATX upon successful transfer to ARX. Then ATX will break link an relink. An external MCU should poll this register before accessing any Link control register. 0x00 controls when to send ATX side ARX control registers over the data link to ARX. 0 : ARX control registers free to be used. 1 : ARX control registers may not be accessed Setting RXCSTATE=1 tells ATX to send all ARX control registers values to ARX, and RXSTATE will be reset to 0 by ATX upon successful transfer to ARX. An external MCU should poll this register before accessing any ARX control register. 0x3E LNKCSTATE R/W 0x4B RXCSTATE R/W Table 12-1 : register update registers Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 60 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 13 ELETRICAL SPECIFICATION Conditions: VDD = +3V, VSS = 0V, TA = - 20C to + 80C Symbol Parameter (condition) Notes Min. 2.0 -20 Typ. 3.0 27 Max. 3.6 80 Units V C Operating conditions VDD TEMP Supply voltage Operating temperature Digital input pins VIH VIL HIGH level input voltage LOW level input voltage 0.7 *VDD VSS VDD 0.3*VDD V V Digital output pins VOH VOL IOL_HD IOH_HD HIGH level output voltage (IOH=-0.5mA) LOW level output voltage (IOL=0.5mA) High drive sink current for DO[0] and DO[2] @ VOL= 0.4V High drive source current for DO[1] and DO[3] @ VOH= VDD-0.4V VDD-0.3 VSS 1 1 VDD 0.3 10 10 V V mA mA General electrical specification IPD Supply current in power down mode 4 A General RF conditions fOP f RGFSK fCHANNEL fXTAL Cload fXTAL Operating frequency Frequency deviation GFSK data rate Channel spacing Crystal frequency Crystal load capacitance Crystal frequency tolerance + temperature drift 2 2400 +/-640 4000 4 16 12 2521 MHz kHz kbps MHz MHz pF ppm 3 3 3 8 16 +/-30 RF Transmit mode P RF_0dBm P RF_-5dBm P RF_-10dBm P RF_-20dBm P RFC P RFCR P BW ITX_0dBm ITX_-5dBm ITX_-10dBm ITX-20dBm Maximum output power (TXPWR=3) Maximum output power (TXPWR=2) Maximum output power (TXPWR=1) Maximum output power (TXPWR=0) RF power control range RF power range control resolution 20dB bandwidth for modulated carrier Supply current @ 0dBm output power Supply current @ -5dBm output power Supply current @ -10dBm output power Supply current @ -20dBm output power 4 4 4 4 16 0 -5 -10 -20 20 4000 17 15 14 13 3 0 -5 -12 +/-3 dBm dBm dBm dBm dB dB kHz mA mA mA mA RF Receive mode IRX RXSENS RXMAX Supply current in receive mode Sensitivity at 0.1%BER Maximum received signal 32 -80 0 mA dBm dBm 1 2 3 4 Output pin programmed for high current (register RXPIO) Device operates in the 2400 MHz ISM band (2400-2483 MHz). For further details on crystal specification, please see section 16.2 Antenna load impedance = 100+j175, please see chapter 16 application information Phone +4772898900 Fax +4772898989 April 2005 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Page 61 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer I2S interface timing TI2S tsI2S thI2S tdI2S fMCLK JRMS I2S clock period DATA and WS (input) setup time to CLK DATA and WS (input) hold time from CLK DATA and WS (output) delay from CLK (see also Figure 7-2 andFigure 7-3) 150 20 20 40 ns ns ns ns MCLK (256 FS ) output clock Locking range vs nominal MCLK frequency RMS jitter 0-25kHz 1 -500 250 (see also Figure 7-10) +500 310 ppm ps Slave SPI interface timing TSSCK tsuSSPI thdSSPI tdSSPI tdSSCK tSRD SSCK clock period SMOSI setup time to SSCK SMOSI hold time from SSCK SMISO delay from SSCK SCSN setup time to SSCK SPI slave ready 2 62 10 10 55 10 5 ns ns ns ns ns ms Master SPI interface timing TMSCK tsuMSPI thdMSPI tdMSPI tdMSCK MSCK clock period MMISO setup time to MSCK MMISO hold time from MSCK MMOSI delay from MSCK MCSN setup to MSCK (see also Figure 7-4) 125 55 10 20 30 (see also Figure 7-11 500 ns ns ns ns ns Slave 2-wire interface timing TSSCL tSW2_dsu tSW2_dhd tSW2_od 2-wire clock period SSDA setup time to SSCL SSDA hold time from SSCL SSDA 1->0 delay from SSCL 1000 50 65 170 (see also Figure 7-6) ns ns ns ns Master 2-wire interface timing TMSCL tMW2_dsu tMW2_dhd tMW2_od 2-wire clock period MSDA setup time to MSCL MSDA hold time from MSCL MSDA 1->0 delay from MSCL 1000 60 50 50 ns ns ns ns Table 13-1 NRF24Z1 electrical specification. 1 2 Nominal MCLK frequency is 256 times fS for fS in [32kHz, 44.1kHz, 48kHz] programmable For VDD 3.0V +/-10%, otherwise minimum TSSCK is 124ns (8MHz) Phone +4772898900 Fax +4772898989 April 2005 Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Page 62 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 14 ABSOLUTE MAXIMUM RATINGS Supply Voltages VDD ...............................- 0.3V to + 3.6V VSS ..................................................... 0V Input Voltage VI ..........................- 0.3V to VDD + 0.3V Output Voltage VO .........................- 0.3V to VDD + 0.3V Total Power Dissipation PD (TA =85C) .................................115mW Temperatures Operating temperature............................................ - 20C to + 80C Storage temperature .............................................. - 40C to + 125C Note: Stress exceeding one or more of the limiting values may cause permanent damage to the device. ATTENTION! Electrostatic sensitive device. Observe precaution for handling. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 63 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 15 PACKAGE OUTLINE NRF24Z1 is packaged in a 36 pin 6 by 6 QFN (all dimensions in mm) matt tin plating. Package Type Green QFN36 (6x6 mm) Min typ. Max A 0.8 0.9 A1 0.0 0.02 0.05 A2 0.65 0.69 b 0.18 0.23 0.3 D/E 6 BSC D1/E1 5.75 BSC e 0.5 BSC J 4.47 4.57 4.67 K 4.47 4.57 4.67 L 0.3 0.4 0.5 R 1.735 1.835 1.935 L Figure 15-1 : NRF24Z1 package outline. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 Phone +4772898900 Fax +4772898989 April 2005 Page 64 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 16 APPLICATION INFORMATION 16.1 Antenna I/O The ANT1 & ANT2 output pins provide a balanced RF output to the antenna. The pins must have a DC path to VDD_PA, either via a RF choke or via the center point in a balanced antenna. Differential load impedance between the ANT1 and ANT2 pins, 100+j175, is recommended for maximum output power. Antennas with lower load impedance (for example 50 ) can be matched to NRF24Z1 by using a simple matching network. 16.2 Crystal Specification Tolerance includes initially accuracy and tolerance over temperature and aging. Frequency 16MHz CL 8pF - 16pF ESR 100 C0max 7.0pF Tolerance 30ppm Table 16-1 Crystal specification of NRF24Z1 To achieve a crystal oscillator solution with low power consumption and fast start-up time, it is recommended to specify the crystal with a low value of crystal load capacitance. The crystal load capacitance, CL, is given by: CL = C1 'C 2 ' , C1 '+C 2 ' where C1 ' = C1 + C PCB1 + C I 1 and C 2 ' = C 2 + C PCB 2 + C I 2 C1 and C 2 are SMD capacitors as shown in the application schematics. CPCB1 and CPCB2 are the layout parasitic on the circuit board. CI1 and CI2 are the capacitance seen into the XC1 and XC2 pin respectively; the value is typical 1pF. 16.3 Bias reference resistor A resistor between pin IREF (pin24) and ground sets up the bias reference for the NRF24Z1. A 22 k? (1%) resistor is to be fitted, and changing the value of this resistor will degrade the NRF24Z1 performance directly. 16.4 Internal digital supply de-coupling Pin DVDD (pin15) is a regulated output of the internal digital power supply of NRF24Z1. The pin is purely for de-coupling purposes and only a 33 nF (X7R) capacitor is to be connected. The pin must not be connected to external VDD and can not be used as power supply for external devices. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 65 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 16.5 PCB layout and de-coupling guidelines A well-designed PCB is necessary especially to achieve good RF performance. Keep in mind that a poor layout may lead to loss of performance, or even functionality. A fully qualified RF-layout for the NRF24Z1 and its surrounding components, including antenna matching network, can be downloaded from www.nordicsemi.no. A PCB with a minimum of two layers with ground planes is recommended for optimum performance. The NRF24Z1 DC supply voltage should be de-coupled as close as possible to the VDD pins, see ch.17. It is preferable to mount a large surface mount capacitor (e.g. 4.7F tantalum) in parallel with the smaller value capacitors. The NRF24Z1 supply voltage should be filtered and routed separately from the supply voltages of other circuitry. Long power supply lines on the PCB should be avoided. All device grounds, VDD connections and VDD bypass capacitors must be connected as close as possible to the NRF24Z1 IC. All the VSS pads in a NRF24Z1 layout should be connected directly to a ground plane and one via should be put as close as possible to each of them. Full swing digital data or control signals should not be routed close to the crystal or the power supply lines. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 66 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 17 APPLICATION EXAMPLE The following example shows a NRF24Z1 schematic and layout where the ATX is controlled over SPI by an external MCU and the ARX has a SPI EEPROM attached for stand alone operation. Interfaces that are routed out from NRF24Z1: * Audio: I2S * ATX control: SPI slave * ATX GPIO: DD[1:0] * ATX external interrupt pin (IRQ) * ARX GPIO: DI[3:0], DO[3:0] 17.1 NRF24Z1 schematics VDD C10 1nF C9 10nF IRQ IRQ 36 35 34 33 32 31 30 29 28 U1 NRF24Z1 SMISO SSCK SCSN SMOSI DD1 DD0 SMISO SSCK SCSN SMOSI DD1 DD0 VDD 1 2 3 4 5 6 7 8 9 IRQ/DO[3]/PWM MSCK VSS VDD VSS MMOSI MMISO MCSN MSCL SSEL/DO[2] SMISO/SSDA/DO[1] SSCK/SSCL/DO[0] SCSN/SADR/DI[3] VDD SMOSI/DD[2]/DI[2] DD[1]/DI[1] DD[0]/DI[0] REQ NRF24Z1 QFN36 6x6 MSDA TXSEL VSS IREF VSS_PA ANT2 ANT1 VDD_PA VDD 27 26 25 24 23 22 21 20 19 VDD R2 22kohm C6 1pF L3 3.3nH C7 RF RF 1.5pF VDD L1 3.3nH L2 R3 47kohm R4 47kohm CLK WS DATA SPDIO MCLK DVDD VSS XC2 XC1 C5 1pF 10nH I2S_CLK I2S_WS I2S_DATA I2S_CLK I2S_WS I2S_DATA 10 11 12 13 14 15 16 17 18 C3 2.2nF C4 4.7pF C11 33nF ATX X1 R1 1M C1 15pF C2 15pF Figure 17-1 NRF24Z1 MCU controlled ATX schematic Resistors R3 and R4 are not necessary for device functionality. R3 is added to guarantee that no NRF24Z1 registers are changed if external MCU is resetting. R4 is put in to terminate the NRF24Z1 SPI input to avoid any floating signals if the SPI bus is disabled (power down). Only one resistor on the bus is needed and if MCU MOSI output has internal pull up/down it can be omitted. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 67 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer VDD U2 CSN MISO 1 2 3 4 CS SO WP VSS 25XX640 VCC HOLD SCK SI 8 7 6 5 SCK MOSI R3 VDD VDD C10 1nF C9 10nF VDD 36 35 34 33 32 31 30 29 28 47k U1 NRF24Z1 DO3 DO2 DO1 DO0 DI3 DI2 DI1 DI0 1 2 3 4 5 6 7 8 9 IRQ/DO[3]/PWM MSCK VSS VDD VSS MMOSI MMISO MCSN MSCL SSEL/DO[2] SMISO/SSDA/DO[1] SSCK/SSCL/DO[0] SCSN/SADR/DI[3] VDD SMOSI/DD[2]/DI[2] DD[1]/DI[1] DD[0]/DI[0] REQ NRF24Z1 QFN36 6x6 MSDA TXSEL VSS IREF VSS_PA ANT2 ANT1 VDD_PA VDD 27 26 25 24 23 22 21 20 19 R2 22kohm C6 1pF L3 3.3nH C7 RF RF 1.5pF VDD L1 3.3nH L2 I2S_CLK I2S_WS I2S_DATA I2S_MCLK 10 11 12 13 14 15 16 17 18 CLK WS DATA SPDIO MCLK DVDD VSS XC2 XC1 C5 1pF 10nH C3 2.2nF C4 4.7pF C11 33nF ARX C1 15pF X1 R1 1M C2 15pF Figure 17-2 NRF24Z1 ARX with SPI EEPROM schematic Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 68 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 17.2 NRF24Z1 layout No components in bottom layer Top silk screen Top layer Figure 17-3 : NRF24Z1 ATX PCB layout Bottom layer Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 69 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer No components in bottom layer Top silk screen Top layer Figure 17-4 : NRF24Z1 ARX PCB layout Bottom layer Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 70 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 17.3 NRF24Z1 Bill of Material ATX: Designator C1 C2 C3 C4 C5 C6 C7 C9 C10 C11 L1 L2 L3 R1 R2 R3 R4 U1 Value 15pF 15pF 2.2nF 4.7pF 1pF 1pF 1.5pF 10nF 1nF 33nF 3.3nH 10nH 3.3nH 1M 22kohm 47kohm 47kohm NRF24Z1 Description Capacitor NP0 +/- 5% Capacitor NP0 +/- 5% Capacitor X7R, +/- 10% Capacitor NP0 +/- 5% Capacitor NP0 +/- 0.1 pF Capacitor NP0 +/- 0.1 pF Capacitor NP0 +/0.25pF Capacitor X7R, +/- 10% Capacitor X7R, +/- 10% Capacitor X7R, +/- 10% TOKO LL1608-FS chip inductor series* Inductor Chip, +/- 5% TOKO LL1608-FS chip inductor series* Resistor 5% Resistor 1 % Resistor 5% Resistor 5% 2.4 GHz audio streamer Crystal Cl=9pF, ESR < 100 ohm, stab.+ drift = +/-30ppm, Footprint CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 QFN36L/6x6 X1 16 MHz BT-XTAL Table 17-1 NRF24Z1 ATX BOM * Inductance vs. frequency may differ significantly in inductors with the same value but different part n umbers and/or vendors! Inductor value is usually characterized at 100-250 MHz. But actual value at 2.4 GHz may vary significantly even though the given inductance at 250 MHz is the same. Inductors from other TOKO series and other vendors may well be used, but antenna match performance MUST be verified as inductor value may need to be changed. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 71 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer ARX: Designator C1 C2 C3 C4 C5 C6 C7 C9 C10 C11 L1 L2 L3 R1 R2 R3 U1 U2 X1 15pF 15pF 2.2nF 4.7pF 1pF 1pF 1.5pF 10nF 1nF 33nF 3.3nH 10nH 3.3nH 1M 22kohm 47k NRF24Z1 25XX640 16 MHz Value Description Capacitor NP0 +/-5% Capacitor NP0 +/-5% Capacitor X7R +/-10% Capacitor NP0 +/-5% Capacitor NP0 +/-0.1 pF Capacitor NP0 +/-0.1 pF Capacitor NP0 +/-0.25 pF Capacitor X7R +/-10% Capacitor X7R +/-10% Capacitor X7R +/-10% TOKO LL1608-FS chip inductor series* Chip Inductor, +/-5% TOKO LL1608-FS chip inductor series* Resistor 5% Resistor 1% Resistor 5% 2.4 GHz audio streamer EEPROM Crystal Cl=9pF, ESR < 100 ohm, stab.+ drift = +/-30ppm, Footprint CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CC1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 CR1608-0603 QFN36L/6x6 SO-G8 BT-XTAL Table 17-2 NRF24Z1 ARX BOM * Inductance vs. frequency may differ significantly in inductors with the same value but different part numbers and/or vendors! Inductor value is usually characterized at 100-250 MHz. But actual value at 2.4 GHz may vary significantly even though the given inductance at 250 MHz is the same. Inductors from other TOKO series and other vendors may well be used, but antenna match performance MUST be verified as inductor value may need to be changed. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 72 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 18 REFERENCES For latest version of documents, please visit http://www.nordicsemi.no Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 73 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 19 DEFINITIONS Data sheet status Objective product specification Preliminary product specification Product specification This datasheet contains target specifications for product development. This datasheet contains preliminary data; supplementary data may be published from Nordic Semiconductor ASA later. This datasheet contains final product specifications. Nordic Semiconductor ASA reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Limiting values Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Specifications sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Table 19-1. Definitions. Nordic Semiconductor ASA reserves the right to make changes without further notice to the product to improve reliability, function or design. Nordic Semiconductor does not assume any liability arising out of the application or use of any product or circuits described herein. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Nordic Semiconductor ASA customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Nordic Semiconductor ASA for any damages resulting from such improper use or sale. Preliminary product specification revision date: 2005-04-29 All rights reserved (R). Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder. Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 74 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer 20 YOUR NOTES Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 75 of 76 PRELIMINARY PRODUCT SPECIFICATION NRF24Z1 wireless audio streamer Nordic Semiconductor ASA - World Wide Distributors For Your nearest dealer, please see http://www.nordicsemi.no Main Office: Vestre Rosten 81, N-7075 Tiller, Norway Phone: +47 72 89 89 00, Fax: +47 72 89 89 89 E-mail: nRF@nordicsemi.no Visit the Nordic Semiconductor ASA website at http://www.nordicsemi.no Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway Revision: 2.0 - Phone +4772898900 - Fax +4772898989 April 2005 Page 76 of 76 |
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